Hi
The number of bits used for TAR autoincrement when using
CSW_ADDRINC_PACKED must be at least 10 according to ARM ADI
specifications. Cortex-M3 uses 12 bits (4k blocks) and OMAP35xx uses 10
bits (1k blocks).
This patch adds support for different TAR autotincrement sizes and sets
it to 12 bits for Cortex-M3.
Regards
Magnus
Index: src/target/arm_adi_v5.c
===================================================================
--- src/target/arm_adi_v5.c (revision 2032)
+++ src/target/arm_adi_v5.c (working copy)
@@ -41,6 +41,9 @@
#include "arm_adi_v5.h"
#include "time_support.h"
+/* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
+#define TAR_AUTOINCR_BLOCK (swjdp->tar_autoincr_block)
+
/*
* Transaction Mode:
* swjdp->trans_mode = TRANS_MODE_COMPOSITE;
@@ -467,8 +470,8 @@
while (wcount > 0)
{
- /* Adjust to write blocks within 4K aligned boundaries */
- blocksize = (0x1000 - (0xFFF & address)) >> 2;
+ /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
+ blocksize = (TAR_AUTOINCR_BLOCK - ((TAR_AUTOINCR_BLOCK-1) & address)) >> 2;
if (wcount < blocksize)
blocksize = wcount;
@@ -517,8 +520,8 @@
{
int nbytes;
- /* Adjust to read within 4K block boundaries */
- blocksize = (0x1000 - (0xFFF & address)) >> 1;
+ /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
+ blocksize = (TAR_AUTOINCR_BLOCK - ((TAR_AUTOINCR_BLOCK-1) & address)) >> 2;
if (wcount < blocksize)
blocksize = wcount;
@@ -613,8 +616,8 @@
{
int nbytes;
- /* Adjust to read within 4K block boundaries */
- blocksize = (0x1000 - (0xFFF & address));
+ /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
+ blocksize = (TAR_AUTOINCR_BLOCK - ((TAR_AUTOINCR_BLOCK-1) & address)) >> 2;
if (wcount < blocksize)
blocksize = wcount;
@@ -710,8 +713,8 @@
while (wcount > 0)
{
- /* Adjust to read within 4K block boundaries */
- blocksize = (0x1000 - (0xFFF & address)) >> 2;
+ /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
+ blocksize = (TAR_AUTOINCR_BLOCK - ((TAR_AUTOINCR_BLOCK-1) & address)) >> 2;
if (wcount < blocksize)
blocksize = wcount;
@@ -784,8 +787,8 @@
{
int nbytes;
- /* Adjust to read within 4K block boundaries */
- blocksize = (0x1000 - (0xFFF & address)) >> 1;
+ /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
+ blocksize = (TAR_AUTOINCR_BLOCK - ((TAR_AUTOINCR_BLOCK-1) & address)) >> 2;
if (wcount < blocksize)
blocksize = wcount;
@@ -879,8 +882,8 @@
{
int nbytes;
- /* Adjust to read within 4K block boundaries */
- blocksize = (0x1000 - (0xFFF & address));
+ /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
+ blocksize = (TAR_AUTOINCR_BLOCK - ((TAR_AUTOINCR_BLOCK-1) & address)) >> 2;
if (wcount < blocksize)
blocksize = wcount;
Index: src/target/arm_adi_v5.h
===================================================================
--- src/target/arm_adi_v5.h (revision 2032)
+++ src/target/arm_adi_v5.h (working copy)
@@ -99,8 +99,17 @@
u8 ack;
/* extra tck clocks for memory bus access */
u32 memaccess_tck;
+ /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
+ u32 tar_autoincr_block;
+
} swjdp_common_t;
+/* Accessor function for currently selected DAP-AP number */
+static inline u8 dap_ap_get_select(swjdp_common_t *swjdp)
+{
+ return (u8)( swjdp ->apsel >> 24);
+}
+
/* Internal functions used in the module, partial transactions, use with caution */
extern int dap_dp_write_reg(swjdp_common_t *swjdp, u32 value, u8 reg_addr);
/* extern int swjdp_write_apacc(swjdp_common_t *swjdp, u32 value, u8 reg_addr); */
Index: src/target/cortex_m3.c
===================================================================
--- src/target/cortex_m3.c (revision 2032)
+++ src/target/cortex_m3.c (working copy)
@@ -1579,6 +1579,7 @@
armv7m->swjdp_info.ap_tar_value = -1;
armv7m->swjdp_info.jtag_info = &cortex_m3->jtag_info;
armv7m->swjdp_info.memaccess_tck = 8;
+ armv7m->swjdp_info.tar_autoincr_block = (1<<12); /* Cortex-M3 has 4096 bytes autoincrement range */
/* initialize arch-specific breakpoint handling */
@@ -1599,6 +1600,10 @@
armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target);
+ if((retval = arm_jtag_setup_connection(&cortex_m3->jtag_info)) != ERROR_OK)
+ {
+ return retval;
+ }
if ((retval = arm_jtag_setup_connection(&cortex_m3->jtag_info)) != ERROR_OK)
{
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