On Wednesday 01 July 2009, Zach Welch wrote: > We should be removing (not adding) commands for editor-specific style. > Would you mind purging the patch of these additions?
Done. Updated patch, with new patch comment, attached.
Prepare the DaVinci PLL code to support the version 0x0E module used in newer chips (e.g. dm365): rename the original code so it's specific to version 0x02 PLL modules, and update the dm355evm code to use that new name. Fix two minor bugs in that version 2 code: sysclk3 setup used the sysclk2 divider address (affecting video processing on dm355, no worry for now) and sysclk2 setup had a syntax error. Also minor fixups to dm355evm, mostly to permit use of RTCK. --- tcl/board/dm355evm.cfg | 9 ++++----- tcl/target/davinci.cfg | 14 ++++++-------- 2 files changed, 10 insertions(+), 13 deletions(-) --- a/tcl/board/dm355evm.cfg +++ b/tcl/board/dm355evm.cfg @@ -1,4 +1,3 @@ -# # DM355 EVM board # http://focus.ti.com/docs/toolsw/folders/print/tmdsevm355.html # http://c6000.spectrumdigital.com/evmdm355/ @@ -22,7 +21,7 @@ proc dm355evm_init {} { puts "Initialize DM355 EVM board" # CLKIN = 24 MHz ... can't talk quickly to ARM yet - jtag_khz 1500 + jtag_rclk 1500 ######################## # PLL1 = 432 MHz (/8, x144) @@ -37,10 +36,10 @@ proc dm355evm_init {} { set pll_divs [dict create] dict set pll_divs div3 16 dict set pll_divs div4 8 - pll_setup $addr 144 $pll_divs + pll_v02_setup $addr 144 $pll_divs # ARM is now running at 216 MHz, so JTAG can go faster - jtag_khz 20000 + jtag_rclk 20000 ######################## # PLL2 = 342 MHz (/8, x114) @@ -50,7 +49,7 @@ proc dm355evm_init {} { set addr [dict get $dm355 pllc2] set pll_divs [dict create] dict set pll_divs prediv 8 - pll_setup $addr 114 $pll_divs + pll_v02_setup $addr 114 $pll_divs ######################## # PINMUX --- a/tcl/target/davinci.cfg +++ b/tcl/target/davinci.cfg @@ -31,12 +31,10 @@ proc mmw {reg setbits clearbits} { # For PLLs that don't have a given register (e.g. plldiv8), or where a # given divider is non-programmable, caller provides *NO* config mapping. # -# REVISIT there are minor differences between the PLL controllers. -# Handle those; maybe check the ID register. This version behaves -# for at least the dm355. On dm6446 and dm357 the PLLRST polarity -# is different. On dm365 there are more changes. -# -proc pll_setup {pll_addr mult config} { + +# PLL version 0x02: tested on dm355 +# REVISIT: On dm6446 and dm357 the PLLRST polarity is different. +proc pll_v02_setup {pll_addr mult config} { set pll_ctrl_addr [expr $pll_addr + 0x100] set pll_ctrl [mrw $pll_ctrl_addr] @@ -98,7 +96,7 @@ proc pll_setup {pll_addr mult config} { set go 1 } if { [dict exists $config div2] } { - 1et div [dict get $config div2] + set div [dict get $config div2] set div [expr 0x8000 | ($div - 1)] mww [expr $pll_addr + 0x011c] $div set go 1 @@ -106,7 +104,7 @@ proc pll_setup {pll_addr mult config} { if { [dict exists $config div3] } { set div [dict get $config div3] set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x011c] $div + mww [expr $pll_addr + 0x0120] $div set go 1 } if { [dict exists $config div4] } {
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