Ouch....
I fear a cleanup job to handle proper translation back/forth
between mode number and enums....
This bug only reared it's head on i.MX27 arm926ejs.
armv4_5_number_to_mode() will encounter an unknown arm
mode for i.MX27 arm926ejs mode number to
enum translation which put me onto the trail of this problem.....
A few suspect sites are marked out in the attached patch.
--
Øyvind Harboe
Embedded software and hardware consulting services
http://www.zylin.com
### Eclipse Workspace Patch 1.0
#P openocd
Index: src/target/xscale.c
===================================================================
--- src/target/xscale.c (revision 2478)
+++ src/target/xscale.c (working copy)
@@ -1061,13 +1061,7 @@
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
LOG_DEBUG("cpsr: 0x%8.8" PRIx32 "", buffer[9]);
- armv4_5->core_mode = buffer[9] & 0x1f;
- if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
- {
- target->state = TARGET_UNKNOWN;
- LOG_ERROR("cpsr contains invalid mode value - communication
failure");
- return ERROR_TARGET_FAILURE;
- }
+ armv4_5->core_mode = armv4_5_number_to_mode(buffer[9] & 0x1f);
LOG_DEBUG("target entered debug state in %s mode",
armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
if (buffer[9] & 0x20)
Index: src/target/arm7_9_common.c
===================================================================
--- src/target/arm7_9_common.c (revision 2478)
+++ src/target/arm7_9_common.c (working copy)
@@ -1409,14 +1409,7 @@
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
- armv4_5->core_mode = cpsr & 0x1f;
-
- if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
- {
- target->state = TARGET_UNKNOWN;
- LOG_ERROR("cpsr contains invalid mode value - communication
failure");
- return ERROR_TARGET_FAILURE;
- }
+ armv4_5->core_mode = armv4_5_number_to_mode(cpsr & 0x1f);
LOG_DEBUG("target entered debug state in %s mode",
armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
Index: src/target/armv4_5.c
===================================================================
--- src/target/armv4_5.c (revision 2478)
+++ src/target/armv4_5.c (working copy)
@@ -223,7 +223,7 @@
if (armv4_5_target->core_mode != (enum armv4_5_mode)(value &
0x1f))
{
LOG_DEBUG("changing ARM core mode to '%s'",
armv4_5_mode_strings[armv4_5_mode_to_number(value & 0x1f)]);
- armv4_5_target->core_mode = value & 0x1f;
+ armv4_5_target->core_mode =
armv4_5_number_to_mode(value & 0x1f);
armv4_5_target->write_core_reg(target, 16,
ARMV4_5_MODE_ANY, value);
}
}
@@ -598,7 +598,7 @@
if (armv4_5_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
{
LOG_DEBUG("setting core_mode: 0x%2.2x",
armv4_5_algorithm_info->core_mode);
- buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value,
0, 5, armv4_5_algorithm_info->core_mode);
+ buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value,
0, 5, armv4_5_mode_to_number(armv4_5_algorithm_info->core_mode));
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
}
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