Change layout of Thumb disassembly to work better with Thumb2:
- Move opcode byte left, allow space for four bytes:
* after address, two spaces not one tab (taking 6 spaces)
* after 2-byte opcode, four spaces before tab
- Also, after opcode use a tab not a space
Sample output (after some patches decoding a few 32-bit instructions)::
0x00003e5a 0xf4423200 ORR r2, r2, #131072 ; 0x20000
0x00003e5e 0x601a STR r2, [r3, #0x0]
0x00003e60 0x2800 CMP r0, #0x00
0x00003e62 0xd1f3 BNE 0x00003e4c
0x00003e64 0xf008fa38 BL 0x0000c2d8
The affected lines of code now wrap at sane margins too.
---
src/target/arm_disassembler.c | 112 +++++++++++++++++++++++++++-------------
1 file changed, 76 insertions(+), 36 deletions(-)
Change layout of Thumb disassembly to work better with Thumb2:
- Move opcode byte left, allow space for four bytes:
* after address, two spaces not one tab (taking 6 spaces)
* after 2-byte opcode, four spaces before tab
- Also, after opcode use a tab not a space
Sample output (after some patches decoding a few 32-bit instructions)::
0x00003e5a 0xf4423200 ORR r2, r2, #131072 ; 0x20000
0x00003e5e 0x601a STR r2, [r3, #0x0]
0x00003e60 0x2800 CMP r0, #0x00
0x00003e62 0xd1f3 BNE 0x00003e4c
0x00003e64 0xf008fa38 BL 0x0000c2d8
The affected lines of code now wrap at sane margins too.
---
src/target/arm_disassembler.c | 112 +++++++++++++++++++++++++++-------------
1 file changed, 76 insertions(+), 36 deletions(-)
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -1363,7 +1363,9 @@ int evaluate_b_bl_blx_thumb(uint16_t opc
}
/* TODO: deals correctly with dual opcodes BL/BLX ... */
- snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s 0x%8.8" PRIx32 , address, opcode,mnemonic, target_address);
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \t%s\t0x%8.8" PRIx32,
+ address, opcode,mnemonic, target_address);
instruction->info.b_bl_bx_blx.reg_operand = -1;
instruction->info.b_bl_bx_blx.target_address = target_address;
@@ -1399,15 +1401,17 @@ int evaluate_add_sub_thumb(uint16_t opco
{
instruction->info.data_proc.variant = 0; /*immediate*/
instruction->info.data_proc.shifter_operand.immediate.immediate = Rm_imm;
- snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s r%i, r%i, #%d",
- address, opcode, mnemonic, Rd, Rn, Rm_imm);
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \t%s\tr%i, r%i, #%d",
+ address, opcode, mnemonic, Rd, Rn, Rm_imm);
}
else
{
instruction->info.data_proc.variant = 1; /*immediate shift*/
instruction->info.data_proc.shifter_operand.immediate_shift.Rm = Rm_imm;
- snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s r%i, r%i, r%i",
- address, opcode, mnemonic, Rd, Rn, Rm_imm);
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \t%s\tr%i, r%i, r%i",
+ address, opcode, mnemonic, Rd, Rn, Rm_imm);
}
return ERROR_OK;
@@ -1451,8 +1455,9 @@ int evaluate_shift_imm_thumb(uint16_t op
instruction->info.data_proc.shifter_operand.immediate_shift.Rm = Rm;
instruction->info.data_proc.shifter_operand.immediate_shift.shift_imm = imm;
- snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s r%i, r%i, #0x%02x" ,
- address, opcode, mnemonic, Rd, Rm, imm);
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \t%s\tr%i, r%i, #0x%02x" ,
+ address, opcode, mnemonic, Rd, Rm, imm);
return ERROR_OK;
}
@@ -1492,8 +1497,9 @@ int evaluate_data_proc_imm_thumb(uint16_
break;
}
- snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s r%i, #0x%02x" ,
- address, opcode, mnemonic, Rd, imm);
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \t%s\tr%i, #0x%02x",
+ address, opcode, mnemonic, Rd, imm);
return ERROR_OK;
}
@@ -1544,18 +1550,28 @@ int evaluate_data_proc_thumb(uint16_t op
if (H1)
{
instruction->type = ARM_BLX;
- snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tBLX r%i", address, opcode, Rm);
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32
+ " 0x%4.4x \tBLX\tr%i",
+ address, opcode, Rm);
}
else
{
instruction->type = ARM_BX;
- snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tBX r%i", address, opcode, Rm);
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32
+ " 0x%4.4x \tBX\tr%i",
+ address, opcode, Rm);
}
}
else
{
instruction->type = ARM_UNDEFINED_INSTRUCTION;
- snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tUNDEFINED INSTRUCTION", address, opcode);
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32
+ " 0x%4.4x \t"
+ "UNDEFINED INSTRUCTION",
+ address, opcode);
}
return ERROR_OK;
break;
@@ -1651,8 +1667,9 @@ int evaluate_data_proc_thumb(uint16_t op
}
}
- snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s r%i, r%i",
- address, opcode, mnemonic, Rd, Rm);
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \t%s\tr%i, r%i",
+ address, opcode, mnemonic, Rd, Rm);
return ERROR_OK;
}
@@ -1665,7 +1682,9 @@ int evaluate_load_literal_thumb(uint16_t
instruction->type = ARM_LDR;
immediate = opcode & 0x000000ff;
- snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tLDR r%i, [PC, #0x%" PRIx32 "]", address, opcode, Rd, immediate*4);
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \tLDR\tr%i, [pc, #0x%" PRIx32 "]",
+ address, opcode, Rd, immediate*4);
instruction->info.load_store.Rd = Rd;
instruction->info.load_store.Rn = 15 /*PC*/;
@@ -1720,7 +1739,9 @@ int evaluate_load_store_reg_thumb(uint16
break;
}
- snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s r%i, [r%i, r%i]", address, opcode, mnemonic, Rd, Rn, Rm);
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \t%s\tr%i, [r%i, r%i]",
+ address, opcode, mnemonic, Rd, Rn, Rm);
instruction->info.load_store.Rd = Rd;
instruction->info.load_store.Rn = Rn;
@@ -1764,7 +1785,9 @@ int evaluate_load_store_imm_thumb(uint16
shift = 0;
}
- snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s%c r%i, [r%i, #0x%" PRIx32 "]", address, opcode, mnemonic, suffix, Rd, Rn, offset << shift);
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \t%s%c\tr%i, [r%i, #0x%" PRIx32 "]",
+ address, opcode, mnemonic, suffix, Rd, Rn, offset << shift);
instruction->info.load_store.Rd = Rd;
instruction->info.load_store.Rn = Rn;
@@ -1793,7 +1816,9 @@ int evaluate_load_store_stack_thumb(uint
mnemonic = "STR";
}
- snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s r%i, [SP, #0x%" PRIx32 "]", address, opcode, mnemonic, Rd, offset*4);
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \t%s\tr%i, [SP, #0x%" PRIx32 "]",
+ address, opcode, mnemonic, Rd, offset*4);
instruction->info.load_store.Rd = Rd;
instruction->info.load_store.Rn = 13 /*SP*/;
@@ -1825,7 +1850,9 @@ int evaluate_add_sp_pc_thumb(uint16_t op
Rn = 15;
}
- snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tADD r%i, %s, #0x%" PRIx32 "", address, opcode, Rd,reg_name, imm*4);
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \tADD\tr%i, %s, #0x%" PRIx32,
+ address, opcode, Rd, reg_name, imm * 4);
instruction->info.data_proc.variant = 0 /* immediate */;
instruction->info.data_proc.Rd = Rd;
@@ -1853,7 +1880,9 @@ int evaluate_adjust_stack_thumb(uint16_t
mnemonic = "ADD";
}
- snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s SP, #0x%" PRIx32 "", address, opcode, mnemonic, imm*4);
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \t%s\tSP, #0x%" PRIx32,
+ address, opcode, mnemonic, imm*4);
instruction->info.data_proc.variant = 0 /* immediate */;
instruction->info.data_proc.Rd = 13 /*SP*/;
@@ -1869,7 +1898,9 @@ int evaluate_breakpoint_thumb(uint16_t o
instruction->type = ARM_BKPT;
- snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tBKPT 0x%02" PRIx32 "", address, opcode, imm);
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \tBKPT\t0x%02" PRIx32 "",
+ address, opcode, imm);
return ERROR_OK;
}
@@ -1930,9 +1961,11 @@ int evaluate_load_store_multiple_thumb(u
if (reg_names_p > reg_names)
reg_names_p[-2] = '\0';
else /* invalid op : no registers */
- reg_names[0] = '\0';
+ reg_names[0] = '\0';
- snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s %s{%s}", address, opcode, mnemonic, ptr_name,reg_names);
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \t%s\t%s{%s}",
+ address, opcode, mnemonic, ptr_name, reg_names);
instruction->info.load_store_multiple.register_list = reg_list;
instruction->info.load_store_multiple.Rn = Rn;
@@ -1951,14 +1984,16 @@ int evaluate_cond_branch_thumb(uint16_t
{
instruction->type = ARM_SWI;
snprintf(instruction->text, 128,
- "0x%8.8" PRIx32 "\t0x%4.4x\tSVC 0x%02" PRIx32,
+ "0x%8.8" PRIx32 " 0x%4.4x \tSVC\t0x%02" PRIx32,
address, opcode, offset);
return ERROR_OK;
}
else if (cond == 0xe)
{
instruction->type = ARM_UNDEFINED_INSTRUCTION;
- snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tUNDEFINED INSTRUCTION", address, opcode);
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \tUNDEFINED INSTRUCTION",
+ address, opcode);
return ERROR_OK;
}
@@ -1968,8 +2003,10 @@ int evaluate_cond_branch_thumb(uint16_t
target_address = address + 4 + (offset << 1);
- snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tB%s 0x%8.8" PRIx32 , address, opcode,
- arm_condition_strings[cond], target_address);
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%4.4x \tB%s\t0x%8.8" PRIx32,
+ address, opcode,
+ arm_condition_strings[cond], target_address);
instruction->type = ARM_B;
instruction->info.b_bl_bx_blx.reg_operand = -1;
@@ -1987,7 +2024,7 @@ static int evaluate_cb_thumb(uint16_t op
offset |= (opcode & 0x0200) >> 4;
snprintf(instruction->text, 128,
- "0x%8.8" PRIx32 "\t0x%4.4x\tCB%sZ r%d, 0x%8.8" PRIx32,
+ "0x%8.8" PRIx32 " 0x%4.4x \tCB%sZ\tr%d, 0x%8.8" PRIx32,
address, opcode,
(opcode & 0x0800) ? "N" : "",
opcode & 0x7, address + 4 + (offset << 1));
@@ -1999,7 +2036,7 @@ static int evaluate_extend_thumb(uint16_
arm_instruction_t *instruction)
{
snprintf(instruction->text, 128,
- "0x%8.8" PRIx32 "\t0x%4.4x\t%cXT%c r%d, r%d",
+ "0x%8.8" PRIx32 " 0x%4.4x \t%cXT%c\tr%d, r%d",
address, opcode,
(opcode & 0x0080) ? 'U' : 'S',
(opcode & 0x0040) ? 'B' : 'H',
@@ -2012,7 +2049,7 @@ static int evaluate_cps_thumb(uint16_t o
arm_instruction_t *instruction)
{
snprintf(instruction->text, 128,
- "0x%8.8" PRIx32 "\t0x%4.4x\tCPSI%c %s%s",
+ "0x%8.8" PRIx32 " 0x%4.4x \tCPSI%c\t%s%s",
address, opcode,
(opcode & 0x0010) ? 'D' : 'E',
(opcode & 0x0002) ? "I" : "",
@@ -2038,7 +2075,7 @@ static int evaluate_byterev_thumb(uint16
break;
}
snprintf(instruction->text, 128,
- "0x%8.8" PRIx32 "\t0x%4.4x\tREV%s r%d, r%d",
+ "0x%8.8" PRIx32 " 0x%4.4x \tREV%s\tr%d, r%d",
address, opcode, suffix,
opcode & 0x7, (opcode >> 3) & 0x7);
@@ -2072,7 +2109,7 @@ static int evaluate_hint_thumb(uint16_t
}
snprintf(instruction->text, 128,
- "0x%8.8" PRIx32 "\t0x%4.4x\t%s",
+ "0x%8.8" PRIx32 " 0x%4.4x \t%s",
address, opcode, hint);
return ERROR_OK;
@@ -2092,7 +2129,7 @@ static int evaluate_ifthen_thumb(uint16_
x = (opcode & 0x08) ? "T" : "E";
snprintf(instruction->text, 128,
- "0x%8.8" PRIx32 "\t0x%4.4x\tIT%s%s%s %s",
+ "0x%8.8" PRIx32 " 0x%4.4x \tIT%s%s%s\t%s",
address, opcode,
x, y, z, arm_condition_strings[cond]);
@@ -2201,7 +2238,7 @@ int thumb_evaluate_opcode(uint16_t opcod
instruction->type = ARM_UNDEFINED_INSTRUCTION;
snprintf(instruction->text, 128,
- "0x%8.8" PRIx32 "\t0x%4.4x\tUNDEFINED INSTRUCTION",
+ "0x%8.8" PRIx32 " 0x%4.4x \tUNDEFINED INSTRUCTION",
address, opcode);
return ERROR_OK;
}
@@ -2224,7 +2261,10 @@ int thumb_evaluate_opcode(uint16_t opcod
if ((opcode & 0xf801) == 0xe801)
{
instruction->type = ARM_UNDEFINED_INSTRUCTION;
- snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8x\tUNDEFINED INSTRUCTION", address, opcode);
+ snprintf(instruction->text, 128,
+ "0x%8.8" PRIx32 " 0x%8.8x\t"
+ "UNDEFINED INSTRUCTION",
+ address, opcode);
return ERROR_OK;
}
else
@@ -2282,7 +2322,7 @@ int thumb2_opcode(target_t *target, uint
LOG_DEBUG("Can't decode 32-bit Thumb2 yet (opcode=%08x)", opcode);
snprintf(instruction->text, 128,
- "0x%8.8" PRIx32 "\t0x%8.8x\t... 32-bit Thumb2 ...",
+ "0x%8.8" PRIx32 " 0x%8.8x\t... 32-bit Thumb2 ...",
address, opcode);
return ERROR_OK;
}
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