Index: cortex_m3.c
===================================================================
--- cortex_m3.c	(revision 2548)
+++ cortex_m3.c	(working copy)
@@ -1274,28 +1274,9 @@
 	}
 	else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core register */
 	{
-		/* read other registers */
+		/* read spec20 */
 		cortexm3_dap_read_coreregister_u32(swjdp, value, 20);
 
-		switch (num)
-		{
-			case 19:
-				*value = buf_get_u32((uint8_t*)value, 0, 8);
-				break;
-
-			case 20:
-				*value = buf_get_u32((uint8_t*)value, 8, 8);
-				break;
-
-			case 21:
-				*value = buf_get_u32((uint8_t*)value, 16, 8);
-				break;
-
-			case 22:
-				*value = buf_get_u32((uint8_t*)value, 24, 8);
-				break;
-		}
-
 		LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
 	}
 	else
@@ -1339,29 +1320,7 @@
 	}
 	else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core register */
 	{
-		/* write other registers */
-
-		cortexm3_dap_read_coreregister_u32(swjdp, &reg, 20);
-
-		switch (num)
-		{
-			case 19:
-				buf_set_u32((uint8_t*)&reg, 0, 8, value);
-				break;
-
-			case 20:
-				buf_set_u32((uint8_t*)&reg, 8, 8, value);
-				break;
-
-			case 21:
-				buf_set_u32((uint8_t*)&reg, 16, 8, value);
-				break;
-
-			case 22:
-				buf_set_u32((uint8_t*)&reg, 24, 8, value);
-				break;
-		}
-
+		/* write spec20 */
 		cortexm3_dap_write_coreregister_u32(swjdp, reg, 20);
 
 		LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);