Hello!
I'm having troubles working with a Samsung s3c2450 (arm926ejs core). Setup
is minimal, just OpenOCD (svn 2555) and Amontec JTAGKey Tiny (no RTCK, but
jtag clock has been set low enough).
The problem is, halt does not work (timeout) and reset halt produces the
following:
> reset halt
JTAG tap: s3c2450.cpu tap/device found: 0x07926f0f (mfg: 0x787, part:
0x7926, ver: 0x0)
JTAG Tap/device matched
WARNING: unknown debug reason: 0x0
invalid mode value encountered 20
cpsr contains invalid mode value - communication failure
Runtime error, file "embedded:startup.tcl", line 222:
expected return code but got 'TARGET: s3c2450.cpu - Not halted'
in procedure 'ocd_process_reset'
called at file "embedded:startup.tcl", line 204
called at file "embedded:startup.tcl", line 205
called at file "embedded:startup.tcl", line 221
Runtime error, file "command.c", line 469:
also:
> reset
JTAG tap: s3c2450.cpu tap/device found: 0x07926f0f (mfg: 0x787, part:
0x7926, ver: 0x0)
JTAG Tap/device matched
WARNING: unknown debug reason: 0x0
invalid mode value encountered 20
cpsr contains invalid mode value - communication failure
Note that both commands worked fine before the boot device (a NAND flash)
was programmed with the steploader, and they still works on "clean" targets.
>From that point on, halt and reset halt stopped working. Maybe there is some
internal boot ROM code which alters ICE operation - but at the moment I have
no information.
Note also:
- the target boots (some messages on a debug UART are shown), but *only*
with no JTAG interface connected - and TRST pulled by SRST
- if JTAG interface is connected, then it doesn't boot at all
My intention and need is that of halting the core just out of reset, but
nope. I'm still waiting for further documentation from Samsung (if
available, who knows... support here is far from excellent) about JTAG
operation - specifically, I've also asked for SRST/TRST relationship that
may affect debug operation. In the meanwhile, I lurked in the code to check
out halt operation and did some tests altering the SRST/TRST
activation/deactivation sequence in relation to debug request and vector
catching - but, again, nope.
I can do some further (dirtier) investigations, but I'm wondering if this
issue has already been addressed somehow for some other target...
Keep investigating!
Regards,
Stefano Voulaz
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