I have a couple questions about tcl:
1. How do you make variables defined as global (see c100regs.tcl &
c100helper.tcl) visible in procedures? I would like to reuse defines in
c100regs.tcl. Otherwise, I need to define them every time I want to use
them. I tried 'global' but it does not work.
2. How to I transfer register (say cpsr or r0) to a tcl variable
(similar to memory -> tcl in mmw())?
3. I can't add comments wth # at the same line as the tcl command. This
is not a big deal but it would be nice to have.
Thanks,
Michal
# mrw,mmw from davinci.cfg
# mrw: "memory read word", returns value of $reg
proc mrw {reg} {
set value ""
ocd_mem2array value 32 $reg 1
return $value(0)
}
# mmw: "memory modify word", updates value of $reg
# $reg <== ((value & ~$clearbits) | $setbits)
proc mmw {reg setbits clearbits} {
set old [mrw $reg]
set new [expr ($old & ~$clearbits) | $setbits]
mww $reg $new
}
proc setupNOR {} {
puts "Setting up NOR: 16MB, CS0"
# this is taken from u-boot/boards/mindspeed/ooma-darwin/board.c:nor_hw_init()
# this really belongs to c100regs.tcl
# can't get the global var. working
set APB_BASEADDR 0x10000000
set EBUS_BASEADDR [expr $APB_BASEADDR + 0x1A0000]
set EX_CSEN_REG [expr $EBUS_BASEADDR + 0x04]
set EX_CS0_SEG_REG [expr $EBUS_BASEADDR + 0x08]
set EX_CS0_CFG_REG [expr $EBUS_BASEADDR + 0x1C]
set EX_CS0_TMG1_REG [expr $EBUS_BASEADDR + 0x30]
set EX_CS0_TMG2_REG [expr $EBUS_BASEADDR + 0x44]
set EX_CS0_TMG3_REG [expr $EBUS_BASEADDR + 0x58]
set EX_CLOCK_DIV_REG [expr $EBUS_BASEADDR + 0x6C]
set EX_MFSM_REG [expr $EBUS_BASEADDR + 0x100]
set EX_MFSM_REG [expr $EBUS_BASEADDR + 0x100]
set EX_CSFSM_REG [expr $EBUS_BASEADDR + 0x104]
set EX_WRFSM_REG [expr $EBUS_BASEADDR + 0x108]
set EX_RDFSM_REG [expr $EBUS_BASEADDR + 0x10C]
# /* set GPIO5 as output */
# SoC_gpio_cfg(5, GPIO_TYPE_OUTPUT);
#
# /* Select lower 8MiB of flash device */
# SoC_gpio_set_0(SoC_gpio_mask(5));
# *(volatile u32 *)EX_CS0_SEG_REG = 0x7FF;
# /* adjust EXP bus configuration registers */
# *(volatile u32 *)EX_CLOCK_DIV_REG = 0x5;
# *(volatile u32 *)EX_CS0_TMG1_REG = 0x03034006;
# *(volatile u32 *)EX_CS0_TMG2_REG = 0x04040002;
# enable Expansion Bus Clock + CS0 (NOR)
mww $EX_CSEN_REG 0x3
# set the address space for CS0=16MB
mww $EX_CS0_SEG_REG 0x7ff
# set the CS0 bus width to 16-bit
mww $EX_CS0_CFG_REG 0x202
# set timings to NOR
mww $EX_CS0_TMG1_REG 0x03034006
mww $EX_CS0_TMG2_REG 0x04040002
#mww $EX_CS0_TMG3_REG
# set EBUS clock 165/5=33MHz
mww $EX_CLOCK_DIV_REG 0x5
# everthing else is OK with default
}
proc showNOR {} {
puts "This is the current NOR setup"
# this really belongs to c100regs.tcl
# can't get the global var. working
set APB_BASEADDR 0x10000000
set EBUS_BASEADDR [expr $APB_BASEADDR + 0x1A0000]
set EX_CSEN_REG [expr $EBUS_BASEADDR + 0x04]
set EX_CS0_SEG_REG [expr $EBUS_BASEADDR + 0x08]
set EX_CS0_CFG_REG [expr $EBUS_BASEADDR + 0x1C]
set EX_CS0_TMG1_REG [expr $EBUS_BASEADDR + 0x30]
set EX_CS0_TMG2_REG [expr $EBUS_BASEADDR + 0x44]
set EX_CS0_TMG3_REG [expr $EBUS_BASEADDR + 0x58]
set EX_CLOCK_DIV_REG [expr $EBUS_BASEADDR + 0x6C]
set EX_MFSM_REG [expr $EBUS_BASEADDR + 0x100]
set EX_MFSM_REG [expr $EBUS_BASEADDR + 0x100]
set EX_CSFSM_REG [expr $EBUS_BASEADDR + 0x104]
set EX_WRFSM_REG [expr $EBUS_BASEADDR + 0x108]
set EX_RDFSM_REG [expr $EBUS_BASEADDR + 0x10C]
puts [format "EX_CSEN_REG (0x%x): 0x%x" $EX_CSEN_REG [mrw $EX_CSEN_REG]]
puts [format "EX_CS0_SEG_REG (0x%x): 0x%x" $EX_CS0_SEG_REG [mrw $EX_CS0_SEG_REG]]
puts [format "EX_CS0_CFG_REG (0x%x): 0x%x" $EX_CS0_CFG_REG [mrw $EX_CS0_CFG_REG]]
puts [format "EX_CS0_TMG1_REG (0x%x): 0x%x" $EX_CS0_TMG1_REG [mrw $EX_CS0_TMG1_REG]]
puts [format "EX_CS0_TMG2_REG (0x%x): 0x%x" $EX_CS0_TMG2_REG [mrw $EX_CS0_TMG2_REG]]
puts [format "EX_CS0_TMG3_REG (0x%x): 0x%x" $EX_CS0_TMG3_REG [mrw $EX_CS0_TMG3_REG]]
puts [format "EX_CLOCK_DIV_REG (0x%x): 0x%x" $EX_CLOCK_DIV_REG [mrw $EX_CLOCK_DIV_REG]]
puts [format "EX_MFSM_REG (0x%x): 0x%x" $EX_MFSM_REG [mrw $EX_MFSM_REG]]
puts [format "EX_CSFSM_REG (0x%x): 0x%x" $EX_CSFSM_REG [mrw $EX_CSFSM_REG]]
puts [format "EX_WRFSM_REG (0x%x): 0x%x" $EX_WRFSM_REG [mrw $EX_WRFSM_REG]]
puts [format "EX_RDFSM_REG (0x%x): 0x%x" $EX_RDFSM_REG [mrw $EX_RDFSM_REG]]
}
proc showGPIO {} {
puts "This is the current GPIO register setup"
# this really belongs to c100regs.tcl
# can't get the global var. working
set APB_BASEADDR 0x10000000
set GPIO_BASEADDR [expr $APB_BASEADDR + 0x070000]
# GPIO outputs register
set GPIO_OUTPUT_REG [expr $GPIO_BASEADDR + 0x00]
# GPIO Output Enable register
set GPIO_OE_REG [expr $GPIO_BASEADDR + 0x04]
set GPIO_HI_INT_ENABLE_REG [expr $GPIO_BASEADDR + 0x08]
set GPIO_LO_INT_ENABLE_REG [expr $GPIO_BASEADDR + 0x0C]
# GPIO input register
set GPIO_INPUT_REG [expr $GPIO_BASEADDR + 0x10]
set APB_ACCESS_WS_REG [expr $GPIO_BASEADDR + 0x14]
set MUX_CONF_REG [expr $GPIO_BASEADDR + 0x18]
set SYSCONF_REG [expr $GPIO_BASEADDR + 0x1C]
set GPIO_ARM_ID_REG [expr $GPIO_BASEADDR + 0x30]
set GPIO_BOOTSTRAP_REG [expr $GPIO_BASEADDR + 0x40]
set GPIO_LOCK_REG [expr $GPIO_BASEADDR + 0x38]
set GPIO_IOCTRL_REG [expr $GPIO_BASEADDR + 0x44]
set GPIO_DEVID_REG [expr $GPIO_BASEADDR + 0x50]
puts [format "GPIO_OUTPUT_REG (0x%x): 0x%x" $GPIO_OUTPUT_REG [mrw $GPIO_OUTPUT_REG]]
puts [format "GPIO_OE_REG (0x%x): 0x%x" $GPIO_OE_REG [mrw $GPIO_OE_REG]]
puts [format "GPIO_HI_INT_ENABLE_REG(0x%x): 0x%x" $GPIO_HI_INT_ENABLE_REG [mrw $GPIO_HI_INT_ENABLE_REG]]
puts [format "GPIO_LO_INT_ENABLE_REG(0x%x): 0x%x" $GPIO_LO_INT_ENABLE_REG [mrw $GPIO_LO_INT_ENABLE_REG]]
puts [format "GPIO_INPUT_REG (0x%x): 0x%x" $GPIO_INPUT_REG [mrw $GPIO_INPUT_REG]]
puts [format "APB_ACCESS_WS_REG (0x%x): 0x%x" $APB_ACCESS_WS_REG [mrw $APB_ACCESS_WS_REG]]
puts [format "MUX_CONF_REG (0x%x): 0x%x" $MUX_CONF_REG [mrw $MUX_CONF_REG]]
puts [format "SYSCONF_REG (0x%x): 0x%x" $SYSCONF_REG [mrw $SYSCONF_REG]]
puts [format "GPIO_ARM_ID_REG (0x%x): 0x%x" $GPIO_ARM_ID_REG [mrw $GPIO_ARM_ID_REG]]
puts [format "GPIO_BOOTSTRAP_REG (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG [mrw $GPIO_BOOTSTRAP_REG]]
puts [format "GPIO_LOCK_REG (0x%x): 0x%x" $GPIO_LOCK_REG [mrw $GPIO_LOCK_REG]]
puts [format "GPIO_IOCTRL_REG (0x%x): 0x%x" $GPIO_IOCTRL_REG [mrw $GPIO_IOCTRL_REG]]
puts [format "GPIO_DEVID_REG (0x%x): 0x%x" $GPIO_DEVID_REG [mrw $GPIO_DEVID_REG]]
}
proc setupGPIO {} {
puts "Setting up GPIO block for Telo"
# This is current setup for Telo:
#GPIO0 reset for FXS-FXO IC, leave as input, the IC has internal pullup
#GPIO1 irq line for FXS-FXO
#GPIO5 addr22 for NOR flash (access to upper 8MB)
#GPIO17 reset for DECT module.
#GPIO29 CS_n for NAND
# this really belongs to c100regs.tcl
# can't get the global var. working
set APB_BASEADDR 0x10000000
set GPIO_BASEADDR [expr $APB_BASEADDR + 0x070000]
# GPIO outputs register
set GPIO_OUTPUT_REG [expr $GPIO_BASEADDR + 0x00]
# GPIO Output Enable register
set GPIO_OE_REG [expr $GPIO_BASEADDR + 0x04]
# set GPIO29=GPIO17=1, GPIO5=0
mww $GPIO_OUTPUT_REG 0x20020000
# enable [as output] GPIO29,GPIO17,GPIO5
mww $GPIO_OE_REG 0x20020020
}
proc highGPIO5 {} {
puts "GPIO5 high"
# can't get the global var. working
set APB_BASEADDR 0x10000000
set GPIO_BASEADDR [expr $APB_BASEADDR + 0x070000]
# GPIO outputs register
set GPIO_OUTPUT_REG [expr $GPIO_BASEADDR + 0x00]
# set GPIO5=1
mmw $GPIO_OUTPUT_REG 0x20 0x0
}
proc lowGPIO5 {} {
puts "GPIO5 low"
# can't get the global var. working
set APB_BASEADDR 0x10000000
set GPIO_BASEADDR [expr $APB_BASEADDR + 0x070000]
# GPIO outputs register
set GPIO_OUTPUT_REG [expr $GPIO_BASEADDR + 0x00]
# set GPIO5=0
mmw $GPIO_OUTPUT_REG 0x0 0x20
}
proc setupPLL_C100 {} {
puts "PLL setup TBD"
}
proc setupDDR2_C100 {} {
puts "DDR2 setup TBD"
}
proc initC100 {} {
# this follows u-boot/cpu/arm1136/start.S
#/*
# remove lock
#*/
# ldr r2, =GPIO_LOCK_REG
# ldr r3, =GPIO_IOCTRL_VAL
# str r3, [r2]
# ldr r2, =GPIO_IOCTRL_REG
# ldr r3, [r2]
#/*
# enable address line A15-A21
#*/
# orr r3, r3, #0xF
set APB_BASEADDR 0x10000000
set GPIO_BASEADDR [expr $APB_BASEADDR + 0x070000]
set GPIO_LOCK_REG [expr $GPIO_BASEADDR + 0x38]
set GPIO_IOCTRL_REG [expr $GPIO_BASEADDR + 0x44]
set GPIO_IOCTRL_VAL 0x55555555
# unlock writing to IOCTRL register
mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL
# enable address lines A15-A21
mmw $GPIO_IOCTRL_REG 0xf 0x0
# /*
# * set the cpu to SVC32 mode
# */
# mrs r0,cpsr
# bic r0,r0,#0x1f
# orr r0,r0,#0xd3
# msr cpsr,r0
# set ARM into supervisor mode
# disable IRQ, FIQ
reg cpsr 0xd3
# /*
# * flush v4 I/D caches
# */
# mov r0, #0
# mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
# mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
#
# /*
# * disable MMU stuff and caches
# */
# mrc p15, 0, r0, c1, c0, 0
# bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
# bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
# orr r0, r0, #0x00000002 @ set bit 2 (A) Align
# orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
# orr r0, r0, #0x00400000 @ set bit 22 (U)
# mcr p15, 0, r0, c1, c0, 0
# This is from bsp_init() in u-boot/boards/mindspeed/ooma-darwin/board.c
# APB init
# // Setting APB Bus Wait states to 1, set post write
# (*(volatile u32*)(APB_ACCESS_WS_REG)) = 0x40;
# AHB init
# // enable all 6 masters for ARAM
# (*(volatile u32*)(ASA_ARAM_TC_CR_REG)) = ASA_TC_REQIDMAEN | ASA_TC_REQTDMEN |ASA_TC_REQIPSECUSBEN |ASA_TC_REQARM0EN | ASA_TC_REQARM1EN |ASA_TC_REQMDMAEN;
# // enable all 6 masters for EBUS
# (*(volatile u32*)(ASA_EBUS_TC_CR_REG)) = ASA_TC_REQIDMAEN | ASA_TC_REQTDMEN |ASA_TC_REQIPSECUSBEN |ASA_TC_REQARM0EN | ASA_TC_REQARM1EN |ASA_TC_REQMDMAEN;
# ARAM init
# // disable pipeline mode in ARAM
# (*(volatile u32*)(MEMCORE_BASEADDR+0x18)) = 1
# PLL init
# HAL_set_amba_clk(CONFIG_SYS_HZ_CLOCK);
# HAL_set_arm_clk(CFG_ARM_CLOCK);
#
# // set PUI
# *(volatile u32*)(CLKCORE_CLKDIV_CNTRL) &= ~(0x1F << PUI_CLKDIV_RATIO_SHIFT);
# *(volatile u32*)(CLKCORE_CLKDIV_CNTRL) |= ((CFG_ARM_CLOCK / 25000000) << PUI_CLKDIV_RATIO_SHIFT);
# *(volatile u32*)(CLKCORE_CLKDIV_CNTRL) &= ~PUI_CLKDIV_BYPASS;
setupPLL_C100
# enable cache
# DDR2 init
setupDDR2_C100
}
# Note that I basically converted
# u-boot/include/asm-arm/arch/comcerto_100.h
# defines
#/* memcore */
#/* device memory base addresses */
#// device memory sizes
#/* ARAM SIZE=64K */
set ARAM_SIZE 0x00010000
set ARAM_BASEADDR 0x0A000000
#/* Hardware Interface Units */
set APB_BASEADDR 0x10000000
#/* APB_SIZE=16M address range */
set APB_SIZE 0x01000000
set EXP_CS0_BASEADDR 0x20000000
set EXP_CS1_BASEADDR 0x24000000
set EXP_CS2_BASEADDR 0x28000000
set EXP_CS3_BASEADDR 0x2C000000
set EXP_CS4_BASEADDR 0x30000000
set DDR_BASEADDR 0x80000000
set TDM_BASEADDR [expr $APB_BASEADDR + 0x000000]
set PHI_BASEADDR [expr $APB_BASEADDR + 0x010000]
set TDMA_BASEADDR [expr $APB_BASEADDR + 0x020000]
set ASA_DDR_BASEADDR [expr $APB_BASEADDR + 0x040000]
set ASA_ARAM_BASEADDR [expr $APB_BASEADDR + 0x048000]
set TIMER_BASEADDR [expr $APB_BASEADDR + 0x050000]
set ASD_BASEADDR [expr $APB_BASEADDR + 0x060000]
set GPIO_BASEADDR [expr $APB_BASEADDR + 0x070000]
set UART0_BASEADDR [expr $APB_BASEADDR + 0x090000]
set UART1_BASEADDR [expr $APB_BASEADDR + 0x094000]
set SPI_BASEADDR [expr $APB_BASEADDR + 0x098000]
set I2C_BASEADDR [expr $APB_BASEADDR + 0x09C000]
set INTC_BASEADDR [expr $APB_BASEADDR + 0x0A0000]
set CLKCORE_BASEADDR [expr $APB_BASEADDR + 0x0B0000]
set PUI_BASEADDR [expr $APB_BASEADDR + 0x0B0000]
set GEMAC_BASEADDR [expr $APB_BASEADDR + 0x0D0000]
set IDMA_BASEADDR [expr $APB_BASEADDR + 0x0E0000]
set MEMCORE_BASEADDR [expr $APB_BASEADDR + 0x0F0000]
set ASA_EBUS_BASEADDR [expr $APB_BASEADDR + 0x100000]
set ASA_AAB_BASEADDR [expr $APB_BASEADDR + 0x108000]
set GEMAC1_BASEADDR [expr $APB_BASEADDR + 0x190000]
set EBUS_BASEADDR [expr $APB_BASEADDR + 0x1A0000]
set MDMA_BASEADDR [expr $APB_BASEADDR + 0x1E0000]
#////////////////////////////////////////////////////////////
#// EBUS block
#////////////////////////////////////////////////////////////
set EX_SWRST_REG [expr $EBUS_BASEADDR + 0x00]
set EX_CSEN_REG [expr $EBUS_BASEADDR + 0x04]
set EX_CS0_SEG_REG [expr $EBUS_BASEADDR + 0x08]
set EX_CS1_SEG_REG [expr $EBUS_BASEADDR + 0x0C]
set EX_CS2_SEG_REG [expr $EBUS_BASEADDR + 0x10]
set EX_CS3_SEG_REG [expr $EBUS_BASEADDR + 0x14]
set EX_CS4_SEG_REG [expr $EBUS_BASEADDR + 0x18]
set EX_CS0_CFG_REG [expr $EBUS_BASEADDR + 0x1C]
set EX_CS1_CFG_REG [expr $EBUS_BASEADDR + 0x20]
set EX_CS2_CFG_REG [expr $EBUS_BASEADDR + 0x24]
set EX_CS3_CFG_REG [expr $EBUS_BASEADDR + 0x28]
set EX_CS4_CFG_REG [expr $EBUS_BASEADDR + 0x2C]
set EX_CS0_TMG1_REG [expr $EBUS_BASEADDR + 0x30]
set EX_CS1_TMG1_REG [expr $EBUS_BASEADDR + 0x34]
set EX_CS2_TMG1_REG [expr $EBUS_BASEADDR + 0x38]
set EX_CS3_TMG1_REG [expr $EBUS_BASEADDR + 0x3C]
set EX_CS4_TMG1_REG [expr $EBUS_BASEADDR + 0x40]
set EX_CS0_TMG2_REG [expr $EBUS_BASEADDR + 0x44]
set EX_CS1_TMG2_REG [expr $EBUS_BASEADDR + 0x48]
set EX_CS2_TMG2_REG [expr $EBUS_BASEADDR + 0x4C]
set EX_CS3_TMG2_REG [expr $EBUS_BASEADDR + 0x50]
set EX_CS4_TMG2_REG [expr $EBUS_BASEADDR + 0x54]
set EX_CS0_TMG3_REG [expr $EBUS_BASEADDR + 0x58]
set EX_CS1_TMG3_REG [expr $EBUS_BASEADDR + 0x5C]
set EX_CS2_TMG3_REG [expr $EBUS_BASEADDR + 0x60]
set EX_CS3_TMG3_REG [expr $EBUS_BASEADDR + 0x64]
set EX_CS4_TMG3_REG [expr $EBUS_BASEADDR + 0x68]
set EX_CLOCK_DIV_REG [expr $EBUS_BASEADDR + 0x6C]
set EX_CLK_EN 0x00000001
set EX_CSBOOT_EN 0x00000002
set EX_CS0_EN 0x00000002
set EX_CS1_EN 0x00000004
set EX_CS2_EN 0x00000008
set EX_CS3_EN 0x00000010
set EX_CS4_EN 0x00000020
set EX_MEM_BUS_8 0x00000000
set EX_MEM_BUS_16 0x00000002
set EX_MEM_BUS_32 0x00000004
set EX_CS_HIGH 0x00000008
set EX_WE_HIGH 0x00000010
set EX_RE_HIGH 0x00000020
set EX_ALE_MODE 0x00000040
set EX_STRB_MODE 0x00000080
set EX_DM_MODE 0x00000100
set EX_NAND_MODE 0x00000200
set EX_RDY_EN 0x00000400
set EX_RDY_EDGE 0x00000800
#////////////////////////////////////////////////////////////
#// GPIO block
#////////////////////////////////////////////////////////////
# GPIO outputs register
set GPIO_OUTPUT_REG [expr $GPIO_BASEADDR + 0x00]
# GPIO Output Enable register
set GPIO_OE_REG [expr $GPIO_BASEADDR + 0x04]
set GPIO_HI_INT_ENABLE_REG [expr $GPIO_BASEADDR + 0x08]
set GPIO_LO_INT_ENABLE_REG [expr $GPIO_BASEADDR + 0x0C]
# GPIO input register
set GPIO_INPUT_REG [expr $GPIO_BASEADDR + 0x10]
set APB_ACCESS_WS_REG [expr $GPIO_BASEADDR + 0x14]
set MUX_CONF_REG [expr $GPIO_BASEADDR + 0x18]
set SYSCONF_REG [expr $GPIO_BASEADDR + 0x1C]
set GPIO_ARM_ID_REG [expr $GPIO_BASEADDR + 0x30]
set GPIO_BOOTSTRAP_REG [expr $GPIO_BASEADDR + 0x40]
set GPIO_LOCK_REG [expr $GPIO_BASEADDR + 0x38]
set GPIO_IOCTRL_REG [expr $GPIO_BASEADDR + 0x44]
set GPIO_DEVID_REG [expr $GPIO_BASEADDR + 0x50]
set GPIO_IOCTRL_A15A16 0x00000001
set GPIO_IOCTRL_A17A18 0x00000002
set GPIO_IOCTRL_A19A21 0x00000004
set GPIO_IOCTRL_TMREVT0 0x00000008
set GPIO_IOCTRL_TMREVT1 0x00000010
set GPIO_IOCTRL_GPBT3 0x00000020
set GPIO_IOCTRL_I2C 0x00000040
set GPIO_IOCTRL_UART0 0x00000080
set GPIO_IOCTRL_UART1 0x00000100
set GPIO_IOCTRL_SPI 0x00000200
set GPIO_IOCTRL_HBMODE 0x00000400
set GPIO_IOCTRL_VAL 0x55555555
set GPIO_0 0x01
set GPIO_1 0x02
set GPIO_2 0x04
set GPIO_3 0x08
set GPIO_4 0x10
set GPIO_5 0x20
set GPIO_6 0x40
set GPIO_7 0x80
set GPIO_RISING_EDGE 1
set GPIO_FALLING_EDGE 2
set GPIO_BOTH_EDGES 3
#////////////////////////////////////////////////////////////
#// UART
#////////////////////////////////////////////////////////////
set UART0_RBR [expr $UART0_BASEADDR + 0x00]
set UART0_THR [expr $UART0_BASEADDR + 0x00]
set UART0_DLL [expr $UART0_BASEADDR + 0x00]
set UART0_IER [expr $UART0_BASEADDR + 0x04]
set UART0_DLH [expr $UART0_BASEADDR + 0x04]
set UART0_IIR [expr $UART0_BASEADDR + 0x08]
set UART0_FCR [expr $UART0_BASEADDR + 0x08]
set UART0_LCR [expr $UART0_BASEADDR + 0x0C]
set UART0_MCR [expr $UART0_BASEADDR + 0x10]
set UART0_LSR [expr $UART0_BASEADDR + 0x14]
set UART0_MSR [expr $UART0_BASEADDR + 0x18]
set UART0_SCR [expr $UART0_BASEADDR + 0x1C]
set UART1_RBR [expr $UART1_BASEADDR + 0x00]
set UART1_THR [expr $UART1_BASEADDR + 0x00]
set UART1_DLL [expr $UART1_BASEADDR + 0x00]
set UART1_IER [expr $UART1_BASEADDR + 0x04]
set UART1_DLH [expr $UART1_BASEADDR + 0x04]
set UART1_IIR [expr $UART1_BASEADDR + 0x08]
set UART1_FCR [expr $UART1_BASEADDR + 0x08]
set UART1_LCR [expr $UART1_BASEADDR + 0x0C]
set UART1_MCR [expr $UART1_BASEADDR + 0x10]
set UART1_LSR [expr $UART1_BASEADDR + 0x14]
set UART1_MSR [expr $UART1_BASEADDR + 0x18]
set UART1_SCR [expr $UART1_BASEADDR + 0x1C]
#////////////////////////////////////////////////////////////
#// CLK + RESET block
#////////////////////////////////////////////////////////////
set CLKCORE_ARM_CLK_CNTRL [expr $CLKCORE_BASEADDR + 0x00]
set CLKCORE_AHB_CLK_CNTRL [expr $CLKCORE_BASEADDR + 0x04]
set CLKCORE_PLL_STATUS [expr $CLKCORE_BASEADDR + 0x08]
set CLKCORE_CLKDIV_CNTRL [expr $CLKCORE_BASEADDR + 0x0C]
set CLKCORE_TDM_CLK_CNTRL [expr $CLKCORE_BASEADDR + 0x10]
set CLKCORE_FSYNC_CNTRL [expr $CLKCORE_BASEADDR + 0x14]
set CLKCORE_CLK_PWR_DWN [expr $CLKCORE_BASEADDR + 0x18]
set CLKCORE_RNG_CNTRL [expr $CLKCORE_BASEADDR + 0x1C]
set CLKCORE_RNG_STATUS [expr $CLKCORE_BASEADDR + 0x20]
set CLKCORE_ARM_CLK_CNTRL2 [expr $CLKCORE_BASEADDR + 0x24]
set CLKCORE_TDM_REF_DIV_RST [expr $CLKCORE_BASEADDR + 0x40]
set ARM_PLL_BY_CTRL 0x80000000
set ARM_AHB_BYP 0x04000000
set PLL_DISABLE 0x02000000
set PLL_CLK_BYPASS 0x01000000
set AHB_PLL_BY_CTRL 0x80000000
set DIV_BYPASS 0x40000000
set SYNC_MODE 0x20000000
set EPHY_CLKDIV_BYPASS 0x00200000
set EPHY_CLKDIV_RATIO_SHIFT 16
set PUI_CLKDIV_BYPASS 0x00004000
set PUI_CLKDIV_SRCCLK 0x00002000
set PUI_CLKDIV_RATIO_SHIFT 8
set PCI_CLKDIV_BYPASS 0x00000020
set PCI_CLKDIV_RATIO_SHIFT 0
set ARM0_CLK_PD 0x00200000
set ARM1_CLK_PD 0x00100000
set EPHY_CLK_PD 0x00080000
set TDM_CLK_PD 0x00040000
set PUI_CLK_PD 0x00020000
set PCI_CLK_PD 0x00010000
set MDMA_AHBCLK_PD 0x00000400
set I2CSPI_AHBCLK_PD 0x00000200
set UART_AHBCLK_PD 0x00000100
set IPSEC_AHBCLK_PD 0x00000080
set TDM_AHBCLK_PD 0x00000040
set USB1_AHBCLK_PD 0x00000020
set USB0_AHBCLK_PD 0x00000010
set GEMAC1_AHBCLK_PD 0x00000008
set GEMAC0_AHBCLK_PD 0x00000004
set PUI_AHBCLK_PD 0x00000002
set HIF_AHBCLK_PD 0x00000001
set ARM1_DIV_BP 0x00001000
set ARM1_DIV_VAL_SHIFT 8
set ARM0_DIV_BP 0x00000010
set ARM0_DIV_VAL_SHIFT 0
set AHBCLK_PLL_LOCK 0x00000002
set FCLK_PLL_LOCK 0x00000001
#// reset block
set BLOCK_RESET_REG [expr $CLKCORE_BASEADDR + 0x100]
set CSP_RESET_REG [expr $CLKCORE_BASEADDR + 0x104]
set RNG_RST 0x1000
set IPSEC_RST 0x0800
set DDR_RST 0x0400
set USB1_PHY_RST 0x0200
set USB0_PHY_RST 0x0100
set USB1_RST 0x0080
set USB0_RST 0x0040
set GEMAC1_RST 0x0020
set GEMAC0_RST 0x0010
set TDM_RST 0x0008
set PUI_RST 0x0004
set HIF_RST 0x0002
set PCI_RST 0x0001
#////////////////////////////////////////////////////////////////
#// DDR CONTROLLER block
#////////////////////////////////////////////////////////////////
set DDR_CONFIG_BASEADDR 0x0D000000
set DENALI_CTL_00_DATA [expr $DDR_CONFIG_BASEADDR + 0x00]
set DENALI_CTL_01_DATA [expr $DDR_CONFIG_BASEADDR + 0x08]
set DENALI_CTL_02_DATA [expr $DDR_CONFIG_BASEADDR + 0x10]
set DENALI_CTL_03_DATA [expr $DDR_CONFIG_BASEADDR + 0x18]
set DENALI_CTL_04_DATA [expr $DDR_CONFIG_BASEADDR + 0x20]
set DENALI_CTL_05_DATA [expr $DDR_CONFIG_BASEADDR + 0x28]
set DENALI_CTL_06_DATA [expr $DDR_CONFIG_BASEADDR + 0x30]
set DENALI_CTL_07_DATA [expr $DDR_CONFIG_BASEADDR + 0x38]
set DENALI_CTL_08_DATA [expr $DDR_CONFIG_BASEADDR + 0x40]
set DENALI_CTL_09_DATA [expr $DDR_CONFIG_BASEADDR + 0x48]
set DENALI_CTL_10_DATA [expr $DDR_CONFIG_BASEADDR + 0x50]
set DENALI_CTL_11_DATA [expr $DDR_CONFIG_BASEADDR + 0x58]
set DENALI_CTL_12_DATA [expr $DDR_CONFIG_BASEADDR + 0x60]
set DENALI_CTL_13_DATA [expr $DDR_CONFIG_BASEADDR + 0x68]
set DENALI_CTL_14_DATA [expr $DDR_CONFIG_BASEADDR + 0x70]
set DENALI_CTL_15_DATA [expr $DDR_CONFIG_BASEADDR + 0x78]
set DENALI_CTL_16_DATA [expr $DDR_CONFIG_BASEADDR + 0x80]
set DENALI_CTL_17_DATA [expr $DDR_CONFIG_BASEADDR + 0x88]
set DENALI_CTL_18_DATA [expr $DDR_CONFIG_BASEADDR + 0x90]
set DENALI_CTL_19_DATA [expr $DDR_CONFIG_BASEADDR + 0x98]
set DENALI_CTL_20_DATA [expr $DDR_CONFIG_BASEADDR + 0xA0]
# 32-bit value
set DENALI_READY_CHECK [expr $DDR_CONFIG_BASEADDR + 0x44]
# 8-bit
set DENALI_WR_DQS [expr $DDR_CONFIG_BASEADDR + 0x5D]
# 8-bit
set DENALI_DQS_OUT [expr $DDR_CONFIG_BASEADDR + 0x5A]
# 8-bit
set DENALI_DQS_DELAY0 [expr $DDR_CONFIG_BASEADDR + 0x4F]
# 8-bit
set DENALI_DQS_DELAY1 [expr $DDR_CONFIG_BASEADDR +0x50]
# 8-bit
set DENALI_DQS_DELAY2 [expr $DDR_CONFIG_BASEADDR +0x51]
# 8-bit
set DENALI_DQS_DELAY3 [expr $DDR_CONFIG_BASEADDR +0x52]
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