Harald Welte wrote:
> Hi Magnus,
>
> On Mon, Aug 31, 2009 at 05:36:11PM +0200, Magnus Lundin wrote:
>
>
>>> dap_ap_select(swjdp, 1);
>>> before the two lines
>>> dap_ap_read_reg_u32(swjdp, 0xFC, &idreg);
>>> dap_ap_read_reg_u32(swjdp, 0xF8, &romaddr);
>>> in ahbap_debugport_init()
>>>
>>>
>>>
Can you place the call to dap_ap_select(swjdp, 1) in
cortex_a8_examine() instead, just after the call to
ahbap_debugport_init() ?
> I see. It's somewhat strange if ARM has all those detailed and fairly
> extensive specifications (and the romtable to discover the debugging
> capabilities), but then no standard way how DBGEN can be set? That's weird.
>
>
It is supposed to be an input to the Cortex_A8 core, so the chip
manufacturer can control debug access without modifying the A8 core.
So have you looked at the OMAP init script, it is something like this:
dap apsel 1
mww 0x54011FB0 0xC5ACCE55 4
# Clear Sticky Power Down status Bit to enable access to the
registers in the Core Power Domain
mdw 0x54011314
# set DBGEN signal
mww 0x5401d030 0x00002000
# enable execute instruction and halting debug mode
mww 0x54011088 0x00006000
# DAP AP 0 is connected to the L3 interconnect and memory bus
dap apsel 0
For you I think this might become:
dap apsel 1
# Unlock the Lock Access to enable writes to debug registers
mww 0x80005FB0 0xC5ACCE55
# Clear Sticky Power Down status Bit to enable access to the
registers in the Core Power Domain
# Se note on PRSR, C_A8 TRM 12.4.21
mdw 0x80005314
# enable execute instruction and halting debug mode
mww 0x80005088 0x00006000
# DAP AP 0 is connected to the L3 interconnect and memory bus
dap apsel 0
Best regards,
Magnus
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