Hi,

I'm trying to debug SAM9-L9260 board /AT91SAM9260 chip/ using the latest GIT 
openocd checkout, FTDI-based dongle and libftdi-0.16. I made the following 
minor fix to the board cfg:
-----------------------------------------------------------------------------
diff --git a/tcl/board/olimex_sam9_l9260.cfg b/tcl/board/olimex_sam9_l9260.cfg
index 935d7cd..5c4714e 100644
--- a/tcl/board/olimex_sam9_l9260.cfg
+++ b/tcl/board/olimex_sam9_l9260.cfg
@@ -26,7 +26,7 @@ $_TARGETNAME configure -event reset-start {

        # RSTC_MR : enable user reset, reset length is 64 slow clock cycles.  MM
        # be enabled... use physical address.
-       arm926ejs mww phys 0xfffffd08 0xa5000501
+       mww phys 0xfffffd08 0xa5000501
 }

 $_TARGETNAME configure -event reset-init {
-----------------------------------------------------------------------------

But OpenOCD reports address translation error when I issue "reset init", even 
though MMU is reported as disabled. Am I doing something wrong? Should I 
replace all "mww" invocations in the board cfg file with "mww phys"? A full 
debug log follows.

Regards,
Dimitar


-----------------------------------------------------------------------------
# ./src/openocd -s ../openocd/tcl -f interface/olimex-arm-usb-tiny-h.cfg -f 
board/olimex_sam9_l9260.cfg -d4
Open On-Chip Debugger 0.3.0-dev-00419-g0b43649 (2009-10-25-13:37)
$URL$
For bug reports, read
        http://openocd.berlios.de/doc/doxygen/bugs.html
User : 5 0 command.c:400 command_print(): debug_level: 3
Debug: 6 0 configuration.c:83 find_file(): found 
../openocd/tcl/interface/olimex-arm-usb-tiny-h.cfg
Debug: 8 0 command.c:68 script_debug(): command - interface
Debug: 9 0 command.c:77 script_debug(): interface - argv[0]=ocd_interface
Debug: 10 0 command.c:77 script_debug(): interface - argv[1]=ft2232
Debug: 12 1 command.c:68 script_debug(): command - ft2232_device_desc
Debug: 13 1 command.c:77 script_debug(): ft2232_device_desc - 
argv[0]=ocd_ft2232_device_desc
Debug: 14 1 command.c:77 script_debug(): ft2232_device_desc - argv[1]=Olimex 
OpenOCD JTAG ARM-USB-TINY-H
Debug: 16 1 command.c:68 script_debug(): command - ft2232_layout
Debug: 17 1 command.c:77 script_debug(): ft2232_layout - 
argv[0]=ocd_ft2232_layout
Debug: 18 1 command.c:77 script_debug(): ft2232_layout - argv[1]=olimex-jtag
Debug: 20 1 command.c:68 script_debug(): command - ft2232_vid_pid
Debug: 21 1 command.c:77 script_debug(): ft2232_vid_pid - 
argv[0]=ocd_ft2232_vid_pid
Debug: 22 1 command.c:77 script_debug(): ft2232_vid_pid - argv[1]=0x15ba
Debug: 23 1 command.c:77 script_debug(): ft2232_vid_pid - argv[2]=0x002a
Debug: 24 1 configuration.c:83 find_file(): found 
../openocd/tcl/board/olimex_sam9_l9260.cfg
Debug: 25 1 configuration.c:83 find_file(): found 
../openocd/tcl/target/at91sam9260.cfg
Debug: 27 1 command.c:68 script_debug(): command - reset_config
Debug: 28 1 command.c:77 script_debug(): reset_config - argv[0]=ocd_reset_config
Debug: 29 1 command.c:77 script_debug(): reset_config - argv[1]=trst_and_srst
Debug: 30 1 command.c:77 script_debug(): reset_config - argv[2]=separate
Debug: 31 1 command.c:77 script_debug(): reset_config - argv[3]=trst_push_pull
Debug: 32 1 command.c:77 script_debug(): reset_config - argv[4]=srst_open_drain
User : 33 1 command.c:400 command_print(): trst_and_srst separate 
srst_gates_jtag trst_push_pull srst_open_drain
Debug: 34 1 tcl.c:246 jim_newtap_cmd(): Creating New Tap, Chip: at91sam9260, 
Tap: cpu, Dotted: at91sam9260.cpu, 8 params
Debug: 35 1 tcl.c:266 jim_newtap_cmd(): Processing option: -irlen
Debug: 36 1 tcl.c:266 jim_newtap_cmd(): Processing option: -ircapture
Debug: 37 1 tcl.c:266 jim_newtap_cmd(): Processing option: -irmask
Debug: 38 1 tcl.c:266 jim_newtap_cmd(): Processing option: -expected-id
Debug: 39 1 core.c:1228 jtag_tap_init(): Created Tap: at91sam9260.cpu @ abs 
position 0, irlen 4, capture: 0x1 mask: 0xf
Debug: 41 1 command.c:68 script_debug(): command - jtag_nsrst_delay
Debug: 42 1 command.c:77 script_debug(): jtag_nsrst_delay - 
argv[0]=ocd_jtag_nsrst_delay
Debug: 43 2 command.c:77 script_debug(): jtag_nsrst_delay - argv[1]=300
User : 44 2 command.c:400 command_print(): jtag_nsrst_delay: 300
Debug: 46 2 command.c:68 script_debug(): command - jtag_ntrst_delay
Debug: 47 2 command.c:77 script_debug(): jtag_ntrst_delay - 
argv[0]=ocd_jtag_ntrst_delay
Debug: 48 2 command.c:77 script_debug(): jtag_ntrst_delay - argv[1]=200
User : 49 2 command.c:400 command_print(): jtag_ntrst_delay: 200
Debug: 51 2 command.c:68 script_debug(): command - jtag_rclk
Debug: 52 2 command.c:77 script_debug(): jtag_rclk - argv[0]=ocd_jtag_rclk
Debug: 53 2 command.c:77 script_debug(): jtag_rclk - argv[1]=3
Debug: 54 2 core.c:1491 jtag_config_rclk(): handle jtag rclk
Debug: 55 2 core.c:1438 jtag_khz_to_speed(): convert khz to interface specific 
speed value
User : 56 2 command.c:400 command_print(): RCLK - adaptive
Debug: 57 2 target.c:4496 jim_target(): Target command params:
Debug: 58 2 target.c:4497 jim_target(): target create at91sam9260.cpu arm926ejs 
-endian little -chain-position at91sam9260.cpu -variant arm926ejs
Debug: 60 2 command.c:68 script_debug(): command - init
Debug: 61 2 command.c:77 script_debug(): init - argv[0]=ocd_init
Debug: 62 3 openocd.c:129 handle_init_command(): target init complete
Debug: 63 3 ft2232.c:2088 ft2232_init(): ft2232 interface using shortest path 
jtag state transitions
Debug: 64 3 ft2232.c:2002 ft2232_init_libftdi(): 'ft2232' interface using 
libftdi with 'olimex-jtag' layout (15ba:002a)
Debug: 65 96 ft2232.c:2046 ft2232_init_libftdi(): current latency timer: 2
Debug: 66 96 ft2232.c:2057 ft2232_init_libftdi(): FTDI chip type: 4 "2232H"
Debug: 67 96 ft2232.c:2426 olimex_jtag_init(): 80 08 1b
Debug: 68 96 ft2232.c:2470 olimex_jtag_init(): 82 09 0f
Info : 69 102 ft2232.c:475 ft2232h_ft4232h_clk_divide_by_5(): max TCK change 
to: 30000 kHz
Debug: 70 102 core.c:1438 jtag_khz_to_speed(): convert khz to interface 
specific speed value
Debug: 71 102 core.c:1442 jtag_khz_to_speed(): have interface set up
Debug: 72 102 ft2232.c:444 ft2232h_ft4232h_adaptive_clocking(): 96
Debug: 73 108 core.c:1438 jtag_khz_to_speed(): convert khz to interface 
specific speed value
Debug: 74 108 core.c:1442 jtag_khz_to_speed(): have interface set up
Info : 75 108 core.c:1281 jtag_interface_init(): RCLK (adaptive clock speed)
Debug: 76 108 openocd.c:136 handle_init_command(): jtag interface init complete
Debug: 77 108 ft2232.c:1351 olimex_jtag_reset(): trst: 0, srst: 0, high_output: 
0x01, high_direction: 0x0f
Debug: 78 109 core.c:702 jtag_add_reset(): SRST line released
Debug: 79 109 core.c:727 jtag_add_reset(): TRST line released
Debug: 80 109 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 82 612 core.c:1292 jtag_init_inner(): Init JTAG chain
Debug: 83 612 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 84 613 core.c:1034 jtag_examine_chain(): DR scan interrogation for 
IDCODE/BYPASS
Debug: 85 613 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset
Info : 86 613 core.c:945 jtag_examine_chain_display(): JTAG tap: 
at91sam9260.cpu tap/device found: 0x0792603f (mfg: 0x01f, part: 0x7926, ver: 
0x0)
Debug: 87 613 core.c:1145 jtag_validate_ircapture(): IR capture validation scan
Debug: 88 614 core.c:1179 jtag_validate_ircapture(): at91sam9260.cpu: IR 
capture 0x01
Debug: 89 614 openocd.c:142 handle_init_command(): jtag init complete
Info : 90 616 embeddedice.c:206 embeddedice_build_reg_cache(): Embedded ICE 
version 6
Debug: 91 618 embeddedice.c:452 embeddedice_write_reg(): 0: 0x00000000
Debug: 92 618 arm7_9_common.c:61 arm7_9_clear_watchpoints(): -
Debug: 93 618 embeddedice.c:452 embeddedice_write_reg(): 12: 0x00000000
Debug: 94 618 embeddedice.c:452 embeddedice_write_reg(): 20: 0x00000000
Debug: 95 618 openocd.c:145 handle_init_command(): jtag examine complete
Debug: 96 618 openocd.c:151 handle_init_command(): flash init complete
Debug: 97 618 openocd.c:155 handle_init_command(): mflash init complete
Debug: 98 618 openocd.c:159 handle_init_command(): NAND init complete
Debug: 99 618 openocd.c:163 handle_init_command(): pld init complete
Debug: 100 618 gdb_server.c:2243 gdb_init(): gdb service for target arm926ejs 
at TCP port 3333
Info : 101 6344 server.c:79 add_connection(): accepting 'telnet' connection 
from 0
Debug: 103 8344 command.c:68 script_debug(): command - reset
Debug: 104 8344 command.c:77 script_debug(): reset - argv[0]=ocd_reset
Debug: 105 8344 command.c:77 script_debug(): reset - argv[1]=init
Debug: 106 8344 target.c:4496 jim_target(): Target command params:
Debug: 107 8344 target.c:4497 jim_target(): target names
Debug: 108 8344 target.c:3595 target_handle_event(): target: (0) 
at91sam9260.cpu (arm926ejs) event: 11 (reset-start) action:
        # At reset, CPU runs at 32.768 kHz.  JTAG frequency must be 6 times 
slower if
        # RCLK is not supported.
        jtag_rclk 5
        halt

        # RSTC_MR : enable user reset, reset length is 64 slow clock cycles.  
MMU may
        # be enabled... use physical address.
        mww phys 0xfffffd08 0xa5000501

Debug: 110 8344 command.c:68 script_debug(): command - jtag_rclk
Debug: 111 8344 command.c:77 script_debug(): jtag_rclk - argv[0]=ocd_jtag_rclk
Debug: 112 8344 command.c:77 script_debug(): jtag_rclk - argv[1]=5
Debug: 113 8344 core.c:1491 jtag_config_rclk(): handle jtag rclk
Debug: 114 8344 core.c:1438 jtag_khz_to_speed(): convert khz to interface 
specific speed value
Debug: 115 8344 core.c:1442 jtag_khz_to_speed(): have interface set up
Debug: 116 8344 ft2232.c:444 ft2232h_ft4232h_adaptive_clocking(): 96
Debug: 117 8345 core.c:1438 jtag_khz_to_speed(): convert khz to interface 
specific speed value
Debug: 118 8345 core.c:1442 jtag_khz_to_speed(): have interface set up
User : 119 8345 command.c:400 command_print(): RCLK - adaptive
Debug: 121 8346 command.c:68 script_debug(): command - halt
Debug: 122 8346 command.c:77 script_debug(): halt - argv[0]=ocd_halt
Debug: 123 8346 target.c:2118 handle_halt_command(): -
Debug: 124 8346 arm7_9_common.c:1326 arm7_9_halt(): target->state: running
Debug: 125 8346 embeddedice.c:452 embeddedice_write_reg(): 0: 0x00000002
Debug: 126 8347 embeddedice.c:452 embeddedice_write_reg(): 0: 0x00000005
Debug: 127 8347 embeddedice.c:452 embeddedice_write_reg(): 0: 0x00000005
Debug: 128 8348 arm926ejs.c:364 arm926ejs_examine_debug_reason(): internal 
debug request
Debug: 129 8348 arm7_9_common.c:1436 arm7_9_debug_entry(): target entered debug 
from ARM state
Debug: 130 8349 arm7_9_common.c:1468 arm7_9_debug_entry(): target entered debug 
state in Supervisor mode
Debug: 131 8349 arm7_9_common.c:1491 arm7_9_debug_entry(): r0: 0x020e8cdc
Debug: 132 8349 arm7_9_common.c:1491 arm7_9_debug_entry(): r1: 0x00000000
Debug: 133 8349 arm7_9_common.c:1491 arm7_9_debug_entry(): r2: 0x026bcecc
Debug: 134 8349 arm7_9_common.c:1491 arm7_9_debug_entry(): r3: 0x23f3d484
Debug: 135 8349 arm7_9_common.c:1491 arm7_9_debug_entry(): r4: 0x00000233
Debug: 136 8349 arm7_9_common.c:1491 arm7_9_debug_entry(): r5: 0x020e8e63
Debug: 137 8349 arm7_9_common.c:1491 arm7_9_debug_entry(): r6: 0x00000000
Debug: 138 8349 arm7_9_common.c:1491 arm7_9_debug_entry(): r7: 0x23ed8458
Debug: 139 8349 arm7_9_common.c:1491 arm7_9_debug_entry(): r8: 0x23ed2fdc
Debug: 140 8350 arm7_9_common.c:1491 arm7_9_debug_entry(): r9: 0xdf97e880
Debug: 141 8350 arm7_9_common.c:1491 arm7_9_debug_entry(): r10: 0x23ed8458
Debug: 142 8350 arm7_9_common.c:1491 arm7_9_debug_entry(): r11: 0x0023232b
Debug: 143 8350 arm7_9_common.c:1491 arm7_9_debug_entry(): r12: 0xfffc4000
Debug: 144 8350 arm7_9_common.c:1491 arm7_9_debug_entry(): r13: 0x23ed2f20
Debug: 145 8350 arm7_9_common.c:1491 arm7_9_debug_entry(): r14: 0x23f1c048
Debug: 146 8350 arm7_9_common.c:1491 arm7_9_debug_entry(): r15: 0x23f1c084
Debug: 147 8350 arm7_9_common.c:1497 arm7_9_debug_entry(): entered debug state 
at PC 0x23f1c084
Debug: 148 8353 arm926ejs.c:513 arm926ejs_post_debug_entry(): cp15_control_reg: 
00051078
Debug: 149 8368 arm926ejs.c:534 arm926ejs_post_debug_entry(): D FSR: 
0x00000094, D FAR: 0x2c910704, I FSR: 0x00000000
Debug: 150 8369 target.c:950 target_call_event_callbacks(): target event 4 
(gdb-halt)
Debug: 151 8369 target.c:950 target_call_event_callbacks(): target event 5 
(halted)
User : 152 8369 target.c:1212 target_arch_state(): target state: halted
User : 153 8369 arm926ejs.c:633 arm926ejs_arch_state(): target halted in ARM 
state due to debug-request, current mode: Supervisor
cpsr: 0x200000d3 pc: 0x23f1c084
MMU: disabled, D-Cache: disabled, I-Cache: enabled
Debug: 155 8370 command.c:68 script_debug(): command - mww
Debug: 156 8370 command.c:77 script_debug(): mww - argv[0]=ocd_mww
Debug: 157 8370 command.c:77 script_debug(): mww - argv[1]=phys
Debug: 158 8370 command.c:77 script_debug(): mww - argv[2]=0xfffffd08
Debug: 159 8370 command.c:77 script_debug(): mww - argv[3]=0xa5000501
Debug: 160 8389 embeddedice.c:452 embeddedice_write_reg(): 0: 0x00000004
Debug: 161 8391 embeddedice.c:452 embeddedice_write_reg(): 0: 0x00000005
Debug: 162 8397 core.c:1366 jtag_init_reset(): Initializing with hard TRST+SRST 
reset
Debug: 163 8397 ft2232.c:1351 olimex_jtag_reset(): trst: 1, srst: 0, 
high_output: 0x08, high_direction: 0x0f
Debug: 164 8398 core.c:722 jtag_add_reset(): TRST line asserted
Debug: 165 8398 ft2232.c:1351 olimex_jtag_reset(): trst: 1, srst: 1, 
high_output: 0x02, high_direction: 0x0f
Debug: 166 8398 core.c:697 jtag_add_reset(): SRST line asserted
Debug: 167 8398 ft2232.c:1351 olimex_jtag_reset(): trst: 0, srst: 1, 
high_output: 0x0b, high_direction: 0x0f
Debug: 168 8398 core.c:727 jtag_add_reset(): TRST line released
Debug: 169 8398 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 170 8602 ft2232.c:1351 olimex_jtag_reset(): trst: 0, srst: 0, 
high_output: 0x01, high_direction: 0x0f
Debug: 171 8603 core.c:702 jtag_add_reset(): SRST line released
Debug: 173 8903 core.c:1292 jtag_init_inner(): Init JTAG chain
Debug: 174 8903 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 175 8904 core.c:1034 jtag_examine_chain(): DR scan interrogation for 
IDCODE/BYPASS
Debug: 176 8904 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset
Info : 177 8904 core.c:945 jtag_examine_chain_display(): JTAG tap: 
at91sam9260.cpu tap/device found: 0x0792603f (mfg: 0x01f, part: 0x7926, ver: 
0x0)
Debug: 178 8905 core.c:1145 jtag_validate_ircapture(): IR capture validation 
scan
Debug: 179 8905 core.c:1179 jtag_validate_ircapture(): at91sam9260.cpu: IR 
capture 0x01
Debug: 180 8907 embeddedice.c:452 embeddedice_write_reg(): 0: 0x00000000
Debug: 181 8907 arm7_9_common.c:61 arm7_9_clear_watchpoints(): -
Debug: 182 8908 embeddedice.c:452 embeddedice_write_reg(): 12: 0x00000000
Debug: 183 8908 embeddedice.c:452 embeddedice_write_reg(): 20: 0x00000000
Debug: 184 8908 arm7_9_common.c:1015 arm7_9_assert_reset(): target->state: 
halted
Debug: 185 8908 embeddedice.c:452 embeddedice_write_reg(): 2: 0x00000001
Debug: 186 8908 ft2232.c:1351 olimex_jtag_reset(): trst: 0, srst: 1, 
high_output: 0x0b, high_direction: 0x0f
Debug: 187 8908 core.c:697 jtag_add_reset(): SRST line asserted
Debug: 188 8908 arm7_9_common.c:1106 arm7_9_deassert_reset(): target->state: 
reset
Debug: 189 8964 ft2232.c:1351 olimex_jtag_reset(): trst: 0, srst: 0, 
high_output: 0x01, high_direction: 0x0f
Debug: 190 8964 core.c:702 jtag_add_reset(): SRST line released
Debug: 191 9286 embeddedice.c:452 embeddedice_write_reg(): 0: 0x00000005
Debug: 192 9286 embeddedice.c:452 embeddedice_write_reg(): 0: 0x00000005
Debug: 193 9318 arm926ejs.c:344 arm926ejs_examine_debug_reason(): vector catch 
breakpoint
Debug: 194 9318 arm7_9_common.c:1436 arm7_9_debug_entry(): target entered debug 
from ARM state
Debug: 195 9720 arm7_9_common.c:1468 arm7_9_debug_entry(): target entered debug 
state in Supervisor mode
Debug: 196 9720 arm7_9_common.c:1491 arm7_9_debug_entry(): r0: 0xfffc8010
Debug: 197 9720 arm7_9_common.c:1491 arm7_9_debug_entry(): r1: 0x00000100
Debug: 198 9720 arm7_9_common.c:1491 arm7_9_debug_entry(): r2: 0x00030000
Debug: 199 9720 arm7_9_common.c:1491 arm7_9_debug_entry(): r3: 0x00000001
Debug: 200 9720 arm7_9_common.c:1491 arm7_9_debug_entry(): r4: 0x00300fb4
Debug: 201 9720 arm7_9_common.c:1491 arm7_9_debug_entry(): r5: 0x00300fb0
Debug: 202 9720 arm7_9_common.c:1491 arm7_9_debug_entry(): r6: 0x00000008
Debug: 203 9720 arm7_9_common.c:1491 arm7_9_debug_entry(): r7: 0x23f18000
Debug: 204 9720 arm7_9_common.c:1491 arm7_9_debug_entry(): r8: 0x00008000
Debug: 205 9720 arm7_9_common.c:1491 arm7_9_debug_entry(): r9: 0x23f00000
Debug: 206 9720 arm7_9_common.c:1491 arm7_9_debug_entry(): r10: 0x0001a000
Debug: 207 9720 arm7_9_common.c:1491 arm7_9_debug_entry(): r11: 0x0023232b
Debug: 208 9720 arm7_9_common.c:1491 arm7_9_debug_entry(): r12: 0x00000000
Debug: 209 9720 arm7_9_common.c:1491 arm7_9_debug_entry(): r13: 0x00300d88
Debug: 210 9720 arm7_9_common.c:1491 arm7_9_debug_entry(): r14: 0x00200a58
Debug: 211 9720 arm7_9_common.c:1491 arm7_9_debug_entry(): r15: 0x00000000
Debug: 212 9720 arm7_9_common.c:1497 arm7_9_debug_entry(): entered debug state 
at PC 0x0
Debug: 213 9874 arm926ejs.c:513 arm926ejs_post_debug_entry(): cp15_control_reg: 
00050078
Debug: 214 9936 arm926ejs.c:534 arm926ejs_post_debug_entry(): D FSR: 
0x00000094, D FAR: 0x2c910704, I FSR: 0x00000000
Debug: 215 9976 target.c:950 target_call_event_callbacks(): target event 4 
(gdb-halt)
Debug: 216 9976 target.c:950 target_call_event_callbacks(): target event 5 
(halted)
User : 217 9976 target.c:1212 target_arch_state(): target state: halted
User : 218 9977 arm926ejs.c:633 arm926ejs_arch_state(): target halted in ARM 
state due to breakpoint, current mode: Supervisor
cpsr: 0x000000d3 pc: 0x00000000
MMU: disabled, D-Cache: disabled, I-Cache: disabled
Debug: 219 10004 target.c:3595 target_handle_event(): target: (0) 
at91sam9260.cpu (arm926ejs) event: 20 (reset-init) action:
        mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog

        ##
        # Clock configuration for 99.328 MHz main clock.
        ##
        mww 0xfffffc20 0x00004001 # CKGR_MOR : enable main oscillator, 512 slow 
clock startup
        sleep 20                  # wait 20 ms (need 15.6 ms for startup)
        mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator 
(18.432 MHz)
        sleep 10                  # wait 10 ms
        mww 0xfffffc28 0x2060bf09 # CKGR_PLLAR : 18.432 MHz / 9 * 97 = 198.656 
MHz, 63 slow clock startup
        sleep 20                  # wait 20 ms (need 1.9 ms for startup)
        mww 0xfffffc30 0x00000101 # PMC_MCKR : no scale on proc clock, master 
is proc / 2
        sleep 10                  # wait 10 ms
        mww 0xfffffc30 0x00000102 # PMC_MCKR : switch to PLLA (99.328 MHz)

        # Increase JTAG speed to 6 MHz if RCLK is not supported.
        jtag_rclk 6000

        arm7_9 dcc_downloads enable # Enable faster DCC downloads.

        ##
        # SDRAM configuration for 2 x Samsung K4S561632J-UC75, 4M x 16Bit x 4 
Banks.
        ##
        mww 0xfffff870 0xffff0000 # PIOC_ASR : select peripheral function for 
D15..D31
        mww 0xfffff804 0xffff0000 # PIOC_PDR : disable PIO function for D15..D31

        mww 0xffffef1c 0x00010002 # EBI_CSA : assign EBI CS1 to SDRAM, 
VDDIOMSEL set for +3V3 memory

        mww 0xffffea08 0x85237259 # SDRAMC_CR : configure SDRAM for Samsung 
chips

        mww 0xffffea00 0x1        # SDRAMC_MR : issue NOP command
        mww 0x20000000 0
        mww 0xffffea00 0x2        # SDRAMC_MR : issue an 'All Banks Precharge' 
command
        mww 0x20000000 0
        mww 0xffffea00 0x4        # SDRAMC_MR : issue 8 x 'Auto-Refresh' command
        mww 0x20000000 0
        mww 0xffffea00 0x4
        mww 0x20000000 0
        mww 0xffffea00 0x4
        mww 0x20000000 0
        mww 0xffffea00 0x4
        mww 0x20000000 0
        mww 0xffffea00 0x4
        mww 0x20000000 0
        mww 0xffffea00 0x4
        mww 0x20000000 0
        mww 0xffffea00 0x4
        mww 0x20000000 0
        mww 0xffffea00 0x4
        mww 0x20000000 0
        mww 0xffffea00 0x3        # SDRAMC_MR : issue a 'Load Mode Register' 
command
        mww 0x20000000 0
        mww 0xffffea00 0x0        # SDRAMC_MR : normal mode
        mww 0x20000000 0

        mww 0xffffea04 0x2b6      # SDRAMC_TR : set refresh timer count to 7 us

Debug: 220 10005 log.c:483 keep_alive(): keep_alive() was not invoked in the 
1000ms timelimit (1162). This may cause trouble with GDB connections.
Debug: 223 10005 command.c:68 script_debug(): command - mww
Debug: 224 10005 command.c:77 script_debug(): mww - argv[0]=ocd_mww
Debug: 225 10005 command.c:77 script_debug(): mww - argv[1]=0xfffffd44
Debug: 226 10005 command.c:77 script_debug(): mww - argv[2]=0x00008000
Debug: 227 10186 arm7_9_common.c:2282 arm7_9_read_memory(): address: 
0x00003ffc, size: 0x00000004, count: 0x00000001
Debug: 228 10555 armv4_5_mmu.c:46 armv4_5_mmu_translate_va(): 1st lvl desc: 
d3500f80
Error: 229 10555 armv4_5_mmu.c:51 armv4_5_mmu_translate_va(): Address 
translation failure
Debug: 230 10556 command.c:444 run_command(): Command failed with error code 
-309
User : 231 10556 command.c:646 openocd_jim_vfprintf(): Runtime error, file 
"../openocd/tcl/board/olimex_sam9_l9260.cfg", line 22:
    User : 232 10556 command.c:646 openocd_jim_vfprintf():
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