Only type 1 branch instruction has a condition code, not type 2. Currently they're both tagged with ARM_B which doesn't allow for the distinction.
Signed-off-by: Nicolas Pitre <[email protected]> --- src/target/arm_simulator.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c index c50a52c..27957b2 100644 --- a/src/target/arm_simulator.c +++ b/src/target/arm_simulator.c @@ -317,8 +317,8 @@ int arm_simulate_step_core(target_t *target, uint32_t *dry_run_pc, struct arm_si return retval; instruction_size = 2; - /* check condition code (only for branch instructions) */ - if (instruction.type == ARM_B && + /* check condition code (only for branch (1) instructions) */ + if ((opcode & 0xf000) == 0xd000 && !thumb_pass_branch_condition(sim->get_cpsr(sim, 0, 32), opcode)) { if (dry_run_pc) -- 1.6.5.1.101.g325e5 _______________________________________________ Openocd-development mailing list [email protected] https://lists.berlios.de/mailman/listinfo/openocd-development
