Teach the "armv4_5" register code to understand about the
secure monitor mode, eliminating cloned ARMv7-A support:
- Add the other three shadowed registers to the arrays
- Support another internal mode number (sigh) in mappings
- Add a "core_type" field to "struct arm" to kick this in
- Switch Cortex-A8 to use the standard register code
- Remove that partial ARMv7-A support
- Have the v7-A arch_state() show CPSR, like ARM7/ARM9
- Catch malloc/calloc failures building that register cache
Add comments to show where the Cortex-A8 isn't actually doing
the right thing for register reads/writes, unless core happens
to be in the right mode to start with ...
Add comments to show where the ARM1176 support should kick
in support for this mode, when it eventually switches over
to more standard register support.
Make related ARMv7-A and Cortex-A8 symbols properly static.
---
This just puts the framework in something like the right shape.
The older cores (ARM7, ARM9, and related) should all still
behave. The newer ones (ARM11, Cortex-A8) don't handle
processor modes quite right yet. Also, note that if there
is really a Secure Monitor running, it can prevent some
debug accesses to its state ... access protections are not
part of this update.
src/target/arm11.c | 21 +++++++--
src/target/armv4_5.c | 56 +++++++++++++++++++-----
src/target/armv4_5.h | 12 ++++-
src/target/armv7a.c | 108 ++---------------------------------------------
src/target/armv7a.h | 52 ----------------------
src/target/cortex_a8.c | 76 ++++++++++++++++++---------------
6 files changed, 118 insertions(+), 207 deletions(-)
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -1780,6 +1780,11 @@ static int arm11_init_target(struct comm
struct target *target)
{
/* Initialize anything we can set up without talking to the target */
+
+ /* FIXME Switch to use the standard build_reg_cache() not custom
+ * code. Do it from examine(), after we check whether we're
+ * an arm1176 and thus support the Secure Monitor mode.
+ */
return arm11_build_reg_cache(target);
}
@@ -1787,7 +1792,7 @@ static int arm11_init_target(struct comm
static int arm11_examine(struct target *target)
{
int retval;
-
+ char *type;
FNC_INFO;
struct arm11_common *arm11 = target_to_arm11(target);
@@ -1818,13 +1823,21 @@ static int arm11_examine(struct target *
switch (arm11->device_id & 0x0FFFF000)
{
- case 0x07B36000: LOG_INFO("found ARM1136"); break;
- case 0x07B56000: LOG_INFO("found ARM1156"); break;
- case 0x07B76000: LOG_INFO("found ARM1176"); break;
+ case 0x07B36000:
+ type = "ARM1136";
+ break;
+ case 0x07B56000:
+ type = "ARM1156";
+ break;
+ case 0x07B76000:
+ arm11->arm.core_type = ARM_MODE_MON;
+ type = "ARM1176";
+ break;
default:
LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
return ERROR_FAIL;
}
+ LOG_INFO("found %s", type);
arm11->debug_version = (arm11->didr >> 16) & 0x0F;
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -38,7 +38,8 @@
static const char *armv4_5_core_reg_list[] =
{
- "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",
"r11", "r12", "r13_usr", "lr_usr", "pc",
+ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+ "r8", "r9", "r10", "r11", "r12", "r13_usr", "lr_usr", "pc",
"r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "r13_fiq",
"lr_fiq",
@@ -50,7 +51,9 @@ static const char *armv4_5_core_reg_list
"r13_und", "lr_und",
- "cpsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_abt", "spsr_und"
+ "cpsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_abt", "spsr_und",
+
+ "r13_mon", "lr_mon", "spsr_mon",
};
static const struct {
@@ -139,6 +142,8 @@ int armv4_5_mode_to_number(enum armv4_5_
return 5;
case ARMV4_5_MODE_SYS:
return 6;
+ case ARM_MODE_MON:
+ return 7;
default:
LOG_ERROR("invalid mode value encountered %d", mode);
return -1;
@@ -163,6 +168,8 @@ enum armv4_5_mode armv4_5_number_to_mode
return ARMV4_5_MODE_UND;
case 6:
return ARMV4_5_MODE_SYS;
+ case 7:
+ return ARM_MODE_MON;
default:
LOG_ERROR("mode index out of bounds %d", number);
return ARMV4_5_MODE_ANY;
@@ -218,11 +225,15 @@ static const struct armv4_5_core_reg arm
{16, ARMV4_5_MODE_IRQ, NULL, NULL},
{16, ARMV4_5_MODE_SVC, NULL, NULL},
{16, ARMV4_5_MODE_ABT, NULL, NULL},
- {16, ARMV4_5_MODE_UND, NULL, NULL}
+ {16, ARMV4_5_MODE_UND, NULL, NULL},
+
+ {13, ARM_MODE_MON, NULL, NULL},
+ {14, ARM_MODE_MON, NULL, NULL},
+ {16, ARM_MODE_MON, NULL, NULL},
};
/* map core mode (USR, FIQ, ...) and register number to indizes into the
register cache */
-const int armv4_5_core_reg_map[7][17] =
+const int armv4_5_core_reg_map[8][17] =
{
{ /* USR */
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
@@ -244,6 +255,9 @@ const int armv4_5_core_reg_map[7][17] =
},
{ /* SYS */
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
+ },
+ { /* MON */
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 37, 38, 39,
}
};
@@ -375,29 +389,44 @@ int armv4_5_invalidate_core_regs(struct
struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm
*armv4_5_common)
{
- int num_regs = 37;
+ int num_regs = ARRAY_SIZE(armv4_5_core_reg_list_arch_info);
struct reg_cache *cache = malloc(sizeof(struct reg_cache));
- struct reg *reg_list = malloc(sizeof(struct reg) * num_regs);
- struct armv4_5_core_reg *arch_info = malloc(sizeof(struct
armv4_5_core_reg) * num_regs);
+ struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
+ struct armv4_5_core_reg *arch_info = calloc(num_regs,
+ sizeof(struct armv4_5_core_reg));
int i;
- cache->name = "arm v4/5 registers";
+ if (!cache || !reg_list || !arch_info) {
+ free(cache);
+ free(reg_list);
+ free(arch_info);
+ return NULL;
+ }
+
+ cache->name = "ARM registers";
cache->next = NULL;
cache->reg_list = reg_list;
- cache->num_regs = num_regs;
+ cache->num_regs = 0;
- for (i = 0; i < 37; i++)
+ for (i = 0; i < num_regs; i++)
{
+ /* Skip registers this core doesn't expose */
+ if (armv4_5_core_reg_list_arch_info[i].mode == ARM_MODE_MON
+ && armv4_5_common->core_type != ARM_MODE_MON)
+ continue;
+
+ /* REVISIT handle Cortex-M, which only shadows R13/SP */
+
arch_info[i] = armv4_5_core_reg_list_arch_info[i];
arch_info[i].target = target;
arch_info[i].armv4_5_common = armv4_5_common;
reg_list[i].name = (char *) armv4_5_core_reg_list[i];
reg_list[i].size = 32;
reg_list[i].value = calloc(1, 4);
- reg_list[i].dirty = 0;
- reg_list[i].valid = 0;
reg_list[i].type = &arm_reg_type;
reg_list[i].arch_info = &arch_info[i];
+
+ cache->num_regs++;
}
return cache;
@@ -1015,5 +1044,8 @@ int armv4_5_init_arch_info(struct target
armv4_5->core_state = ARMV4_5_STATE_ARM;
armv4_5->core_mode = ARMV4_5_MODE_USR;
+ /* core_type may be overridden by subtype logic */
+ armv4_5->core_type = ARMV4_5_MODE_ANY;
+
return ERROR_OK;
}
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -56,7 +56,7 @@ typedef enum armv4_5_state
extern char* armv4_5_state_strings[];
-extern const int armv4_5_core_reg_map[7][17];
+extern const int armv4_5_core_reg_map[8][17];
#define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
@@ -89,7 +89,15 @@ struct arm
int common_magic;
struct reg_cache *core_cache;
- int /* armv4_5_mode */ core_mode;
+ /**
+ * Indicates what registers are in the ARM state core register set.
+ * ARMV4_5_MODE_ANY indicates the standard set of 37 registers,
+ * seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three
+ * more registers are shadowed, for "Secure Monitor" mode.
+ */
+ enum armv4_5_mode core_type;
+
+ enum armv4_5_mode core_mode;
enum armv4_5_state core_state;
/** Flag reporting unavailability of the BKPT instruction. */
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -34,108 +34,12 @@
#include <unistd.h>
-char* armv7a_core_reg_list[] =
-{
- "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
- "r8", "r9", "r10", "r11", "r12", "r13_usr", "lr_usr", "pc",
- "r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "r13_fiq",
"lr_fiq",
- "r13_irq", "lr_irq",
- "r13_svc", "lr_svc",
- "r13_abt", "lr_abt",
- "r13_und", "lr_und",
- "cpsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_abt", "spsr_und",
- "r13_mon", "lr_mon", "spsr_mon"
-};
-
-char* armv7a_state_strings[] =
+static const char *armv7a_state_strings[] =
{
"ARM", "Thumb", "Jazelle", "ThumbEE"
};
-struct armv7a_core_reg armv7a_core_reg_list_arch_info[] =
-{
- {0, ARMV4_5_MODE_ANY, NULL, NULL},
- {1, ARMV4_5_MODE_ANY, NULL, NULL},
- {2, ARMV4_5_MODE_ANY, NULL, NULL},
- {3, ARMV4_5_MODE_ANY, NULL, NULL},
- {4, ARMV4_5_MODE_ANY, NULL, NULL},
- {5, ARMV4_5_MODE_ANY, NULL, NULL},
- {6, ARMV4_5_MODE_ANY, NULL, NULL},
- {7, ARMV4_5_MODE_ANY, NULL, NULL},
- {8, ARMV4_5_MODE_ANY, NULL, NULL},
- {9, ARMV4_5_MODE_ANY, NULL, NULL},
- {10, ARMV4_5_MODE_ANY, NULL, NULL},
- {11, ARMV4_5_MODE_ANY, NULL, NULL},
- {12, ARMV4_5_MODE_ANY, NULL, NULL},
- {13, ARMV4_5_MODE_USR, NULL, NULL},
- {14, ARMV4_5_MODE_USR, NULL, NULL},
- {15, ARMV4_5_MODE_ANY, NULL, NULL},
-
- {8, ARMV4_5_MODE_FIQ, NULL, NULL},
- {9, ARMV4_5_MODE_FIQ, NULL, NULL},
- {10, ARMV4_5_MODE_FIQ, NULL, NULL},
- {11, ARMV4_5_MODE_FIQ, NULL, NULL},
- {12, ARMV4_5_MODE_FIQ, NULL, NULL},
- {13, ARMV4_5_MODE_FIQ, NULL, NULL},
- {14, ARMV4_5_MODE_FIQ, NULL, NULL},
-
- {13, ARMV4_5_MODE_IRQ, NULL, NULL},
- {14, ARMV4_5_MODE_IRQ, NULL, NULL},
-
- {13, ARMV4_5_MODE_SVC, NULL, NULL},
- {14, ARMV4_5_MODE_SVC, NULL, NULL},
-
- {13, ARMV4_5_MODE_ABT, NULL, NULL},
- {14, ARMV4_5_MODE_ABT, NULL, NULL},
-
- {13, ARMV4_5_MODE_UND, NULL, NULL},
- {14, ARMV4_5_MODE_UND, NULL, NULL},
-
- {16, ARMV4_5_MODE_ANY, NULL, NULL},
- {16, ARMV4_5_MODE_FIQ, NULL, NULL},
- {16, ARMV4_5_MODE_IRQ, NULL, NULL},
- {16, ARMV4_5_MODE_SVC, NULL, NULL},
- {16, ARMV4_5_MODE_ABT, NULL, NULL},
- {16, ARMV4_5_MODE_UND, NULL, NULL},
-
- {13, ARMV7A_MODE_MON, NULL, NULL},
- {14, ARMV7A_MODE_MON, NULL, NULL},
- {16, ARMV7A_MODE_MON, NULL, NULL}
-};
-
-/* map core mode (USR, FIQ, ...) and register number to indizes into the
register cache */
-int armv7a_core_reg_map[8][17] =
-{
- { /* USR */
- 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
- },
- { /* FIQ */
- 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 15, 32
- },
- { /* IRQ */
- 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 23, 24, 15, 33
- },
- { /* SVC */
- 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 25, 26, 15, 34
- },
- { /* ABT */
- 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 28, 15, 35
- },
- { /* UND */
- 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 29, 30, 15, 36
- },
- { /* SYS */
- 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
- },
- { /* MON */
- /* TODO Fix the register mapping for mon, we need r13_mon,
- * r14_mon and spsr_mon
- */
- 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
- }
-};
-
-void armv7a_show_fault_registers(struct target *target)
+static void armv7a_show_fault_registers(struct target *target)
{
uint32_t dfsr, ifsr, dfar, ifar;
struct armv7a_common *armv7a = target_to_armv7a(target);
@@ -169,16 +73,14 @@ int armv7a_arch_state(struct target *tar
}
LOG_USER("target halted in %s state due to %s, current mode: %s\n"
- "%s: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
+ "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
"MMU: %s, D-Cache: %s, I-Cache: %s",
armv7a_state_strings[armv7a->core_state],
Jim_Nvp_value2name_simple(nvp_target_debug_reason,
target->debug_reason)->name,
arm_mode_name(armv4_5->core_mode),
- armv7a_core_reg_list[armv7a_core_reg_map[
- armv7a_mode_to_number(armv4_5->core_mode)][16]],
- buf_get_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5->core_mode, 16).value, 0, 32),
+ buf_get_u32(armv4_5->core_cache
+ ->reg_list[ARMV4_5_CPSR].value, 0, 32),
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
state[armv7a->armv4_5_mmu.mmu_enabled],
state[armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -45,15 +45,6 @@ typedef enum armv7a_state
ARMV7A_STATE_THUMBEE,
} armv7a_state_t;
-extern char *armv7a_state_strings[];
-
-extern int armv7a_core_reg_map[8][17];
-
-#define ARMV7A_CORE_REG_MODE(cache, mode, num) \
-
cache->reg_list[armv7a_core_reg_map[armv7a_mode_to_number(mode)][num]]
-#define ARMV7A_CORE_REG_MODENUM(cache, mode, num) \
- cache->reg_list[armv7a_core_reg_map[mode][num]]
-
enum
{
ARM_PC = 15,
@@ -102,9 +93,6 @@ struct armv7a_common
struct armv4_5_mmu_common armv4_5_mmu;
struct arm armv4_5_common;
-// int (*full_context)(struct target *target);
-// int (*read_core_reg)(struct target *target, int num, enum armv7a_mode
mode);
-// int (*write_core_reg)(struct target *target, int num, enum armv7a_mode
mode, u32 value);
int (*read_cp15)(struct target *target,
uint32_t op1, uint32_t op2,
uint32_t CRn, uint32_t CRm, uint32_t *value);
@@ -149,44 +137,4 @@ struct reg_cache *armv7a_build_reg_cache
int armv7a_register_commands(struct command_context *cmd_ctx);
int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a);
-/* map psr mode bits to linear number */
-static inline int armv7a_mode_to_number(enum armv7a_mode mode)
-{
- switch (mode)
- {
- case ARMV7A_MODE_USR: return 0; break;
- case ARMV7A_MODE_FIQ: return 1; break;
- case ARMV7A_MODE_IRQ: return 2; break;
- case ARMV7A_MODE_SVC: return 3; break;
- case ARMV7A_MODE_ABT: return 4; break;
- case ARMV7A_MODE_UND: return 5; break;
- case ARMV7A_MODE_SYS: return 6; break;
- case ARMV7A_MODE_MON: return 7; break;
- case ARMV7A_MODE_ANY: return 0; break; /* map MODE_ANY to user
mode */
- default:
- LOG_ERROR("invalid mode value encountered, val %d",
mode);
- return -1;
- }
-}
-
-/* map linear number to mode bits */
-static inline enum armv7a_mode armv7a_number_to_mode(int number)
-{
- switch(number)
- {
- case 0: return ARMV7A_MODE_USR; break;
- case 1: return ARMV7A_MODE_FIQ; break;
- case 2: return ARMV7A_MODE_IRQ; break;
- case 3: return ARMV7A_MODE_SVC; break;
- case 4: return ARMV7A_MODE_ABT; break;
- case 5: return ARMV7A_MODE_UND; break;
- case 6: return ARMV7A_MODE_SYS; break;
- case 7: return ARMV7A_MODE_MON; break;
- default:
- LOG_ERROR("mode index out of bounds");
- return ARMV7A_MODE_ANY;
- }
-};
-
-
#endif /* ARMV4_5_H */
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -480,7 +480,7 @@ static int cortex_a8_resume(struct targe
/* current = 1: continue on current pc, otherwise continue at <address>
*/
resume_pc = buf_get_u32(
- ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+ ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
armv4_5->core_mode, 15).value,
0, 32);
if (!current)
@@ -501,12 +501,12 @@ static int cortex_a8_resume(struct targe
resume_pc |= 0x1;
}
LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
- buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+ buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
armv4_5->core_mode, 15).value,
0, 32, resume_pc);
- ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+ ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
armv4_5->core_mode, 15).dirty = 1;
- ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+ ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
armv4_5->core_mode, 15).valid = 1;
cortex_a8_restore_context(target);
@@ -627,19 +627,21 @@ static int cortex_a8_debug_entry(struct
for (i = 0; i <= ARM_PC; i++)
{
- buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+ buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
armv4_5->core_mode, i).value,
0, 32, regfile[i]);
- ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+ ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
armv4_5->core_mode, i).valid = 1;
- ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+ ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
armv4_5->core_mode, i).dirty = 0;
}
- buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+ buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
armv4_5->core_mode, 16).value,
0, 32, cpsr);
- ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid
= 1;
- ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty
= 0;
+ ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
+ armv4_5->core_mode, 16).valid = 1;
+ ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
+ armv4_5->core_mode, 16).dirty = 0;
/* Fixup PC Resume Address */
if (armv7a->core_state == ARMV7A_STATE_THUMB)
@@ -652,15 +654,15 @@ static int cortex_a8_debug_entry(struct
// ARM state
regfile[ARM_PC] -= 8;
}
- buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+ buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
armv4_5->core_mode, ARM_PC).value,
0, 32, regfile[ARM_PC]);
- ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0)
- .dirty = ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+ ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0)
+ .dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
armv4_5->core_mode, 0).valid;
- ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15)
- .dirty = ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+ ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15)
+ .dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
armv4_5->core_mode, 15).valid;
#if 0
@@ -738,13 +740,13 @@ static int cortex_a8_step(struct target
/* current = 1: continue on current pc, otherwise continue at <address>
*/
if (!current)
{
- buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+ buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
armv4_5->core_mode, ARM_PC).value,
0, 32, address);
}
else
{
- address = buf_get_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+ address = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
armv4_5->core_mode, ARM_PC).value,
0, 32);
}
@@ -756,7 +758,8 @@ static int cortex_a8_step(struct target
handle_breakpoints = 1;
if (handle_breakpoints) {
breakpoint = breakpoint_find(target,
-
buf_get_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+ buf_get_u32(ARMV4_5_CORE_REG_MODE(
+ armv4_5->core_cache,
armv4_5->core_mode, 15).value,
0, 32));
if (breakpoint)
@@ -812,10 +815,11 @@ static int cortex_a8_restore_context(str
for (i = 15; i >= 0; i--)
{
- if (ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+ if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
armv4_5->core_mode, i).dirty)
{
- value =
buf_get_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+ value = buf_get_u32(ARMV4_5_CORE_REG_MODE(
+ armv4_5->core_cache,
armv4_5->core_mode, i).value,
0, 32);
/* TODO Check return values */
@@ -859,13 +863,13 @@ static int cortex_a8_load_core_reg_u32(s
/* Register other than r0 - r14 uses r0 for access */
if (num > 14)
- ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+ ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
armv4_5->core_mode, 0).dirty =
- ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+ ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
armv4_5->core_mode, 0).valid;
- ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+ ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
armv4_5->core_mode, 15).dirty =
- ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+ ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
armv4_5->core_mode, 15).valid;
return ERROR_OK;
@@ -895,9 +899,9 @@ static int cortex_a8_store_core_reg_u32(
if (retval != ERROR_OK)
{
LOG_ERROR("JTAG failure %i", retval);
- ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+ ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
armv4_5->core_mode, num).dirty =
- ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+ ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
armv4_5->core_mode, num).valid;
return ERROR_JTAG_DEVICE_ERROR;
}
@@ -920,6 +924,8 @@ static int cortex_a8_read_core_reg(struc
int retval;
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ /* FIXME cortex may not be in "mode" ... */
+
cortex_a8_dap_read_coreregister_u32(target, &value, num);
if ((retval = jtag_execute_queue()) != ERROR_OK)
@@ -927,28 +933,30 @@ static int cortex_a8_read_core_reg(struc
return retval;
}
- ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
- ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
- buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+ ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
+ ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
+ buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
mode, num).value, 0, 32, value);
return ERROR_OK;
}
-int cortex_a8_write_core_reg(struct target *target, int num,
+static int cortex_a8_write_core_reg(struct target *target, int num,
enum armv4_5_mode mode, uint32_t value)
{
int retval;
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ /* FIXME cortex may not be in "mode" ... */
+
cortex_a8_dap_write_coreregister_u32(target, value, num);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
- ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
- ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
+ ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
+ ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
return ERROR_OK;
}
@@ -1423,6 +1431,8 @@ static void cortex_a8_build_reg_cache(st
struct reg_cache **cache_p =
register_get_last_cache_p(&target->reg_cache);
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ armv4_5->core_type = ARM_MODE_MON;
+
(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
armv4_5->core_cache = (*cache_p);
}
@@ -1493,8 +1503,6 @@ LOG_DEBUG(" ");
// armv4_5->load_core_reg_u32 = cortex_a8_load_core_reg_u32;
// armv4_5->store_core_reg_u32 = cortex_a8_store_core_reg_u32;
-// armv4_5->read_core_reg = armv4_5_read_core_reg; /* this is default */
-// armv4_5->write_core_reg = armv4_5_write_core_reg;
target_register_timer_callback(cortex_a8_handle_target_request, 1, 1,
target);
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