On Wednesday 18 November 2009, Zach Welch wrote: > Very nice. Keep 'em comin'. --Z
Right now ARM11 and Cortex-A8 are somewhat problematic in that they don't support all the "common" ARM base type mechanisms ... and my recent patches are to help address those issues. Add mode changing support to the A8 support, and it'll be in pretty good shape (in that respect). The output from this command will then actually show *different values* for the shadowed registers!! :) ARM11 needs a more substantial overhaul for its register handling. - Dave > On Wed, 2009-11-18 at 16:41 -0700, David Brownell wrote: > > Change the layout to show the "Secure Monitor" registers too, > > when they're present. > > ... > > --- > > Merged this ... sample output, from an ARM9 (without support > > for the Secure Monitor mode): > > > > > arm reg > > System and User mode registers > > r0: 000003e8 r1: 00ff8000 r2: 00000601 r3: 00002800 > > r4: 00000010 r5: 01e11000 r6: 00000001 r7: 01e11000 > > r8: 00000001 r9: 00000002 r10: 00000237 r11: 00ff8000 > > r12: 0000023a sp_usr: 90390944 lr_usr: 238440a9 pc: 00008000 > > cpsr: 000000d3 > > > > FIQ mode shadow registers > > r8_fiq: 601100a2 r9_fiq: 740f0188 r10_fiq: d1d683b4 r11_fiq: 496c1a00 > > r12_fiq: 310549ea sp_fiq: 00007ffc lr_fiq: 0000987c spsr_fiq: 00000010 > > > > Supervisor mode shadow registers > > sp_svc: 00007f24 lr_svc: 00008a20 spsr_svc: 00000010 > > > > Abort mode shadow registers > > sp_abt: 40480085 lr_abt: 4409025c spsr_abt: 00000010 > > > > IRQ mode shadow registers > > sp_irq: 2a720808 lr_irq: 0f8e11c4 spsr_irq: 00000010 > > > > Undefined instruction mode shadow registers > > sp_und: 2f2082f0 lr_und: 2186812c spsr_und: 00000010 _______________________________________________ Openocd-development mailing list [email protected] https://lists.berlios.de/mailman/listinfo/openocd-development
