On Fri, 4 Dec 2009, David Brownell wrote:
> Clean up arm_semihosting() entry a bit, comment some issues and just
> which SVC opcodes are getting intercepted. Microcontroller profile
> cores will need a new entry, since they don't use SVC there (or even
> have an SVC mode).
In that case they use BKPT 0xAB instead of SVC 0xAB. And the
microcontroller profile has only thumb2 mode so no need to bother with
(the non existing) spsr.
> - struct arm *armv4_5 = target_to_armv4_5(target);
> + struct arm *arm = target_to_armv4_5(target);
Wouldn't it be time to s/target_to_armv4_5/target_to_arm/ everywhere?
> + /* Check for PC == 8: Supervisor Call vector
> + * REVISIT: assumes low exception vectors, not hivecs...
> + * safer to test "was this entry from a vector catch".
> + */
There is no universal "vector catch" facility. Some targets might have
to use a breakpoint instead. And hardware breakpoints are precious
resources i.e. Feroceon/Dragonite have only one of those already
involved in single-step support for example. So software breakpoints
are preferable when there is no vector catch.
But yet some targets have the vectors in ROM (or flash) pointing to a
jump table located in RAM. In that case the breakpoint has to be placed
in the jump table instead. So there is more to it than just 0x08 or
0xffff0008. This is why the enabling of semihosting is really
architecture dependent.
> + /* Core-specific code should make sure SPSR is retrieved
> + * when the above checks pass...
> + */
> + if (!arm->spsr->valid)
> + LOG_WARNING("SPSR not valid!");
Better return an error and stop rather than continuing with wrong
information in that case.
Nicolas
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