Sounds good to me. I have given the target directory a wide berth since
you have been working on it. ;)
On Fri, 2009-12-04 at 19:29 -0800, David Brownell wrote:
> I'm committing some renaming patches, which help move the
> stuff in "armv4_5.h" more towards being generic ARM stuff.
>
> Sample patch appended ... they're all equally boring, so
> I won't be posting every one of them. They're done by
> more or less
>
> for F in $(grep -rl OLD src)
> do
> sed -i "s/$OLD/$NEW" $F
> done
>
> with a test build. Any goofage should be easy to find and
> fix, including in your own as-yet-unmerged patches.
>
> - Dave
>
>
> ==============
> flash/arm_nandio.c | 4 ++--
> flash/nor/aduc702x.c | 2 +-
> flash/nor/cfi.c | 4 ++--
> flash/nor/ecos.c | 2 +-
> flash/nor/lpc2000.c | 2 +-
> flash/nor/lpc2900.c | 2 +-
> flash/nor/str7x.c | 2 +-
> flash/nor/str9x.c | 2 +-
> target/arm7_9_common.c | 30 +++++++++++++++---------------
> target/arm_dpm.c | 12 ++++++------
> target/arm_semihosting.c | 2 +-
> target/arm_simulator.c | 28 ++++++++++++++--------------
> target/armv4_5.c | 18 +++++++++---------
> target/armv4_5.h | 6 +++---
> target/cortex_a8.c | 8 ++++----
> target/etm.c | 18 +++++++++---------
> target/feroceon.c | 2 +-
> target/xscale.c | 10 +++++-----
> 18 files changed, 77 insertions(+), 77 deletions(-)
>
>
> --- a/src/flash/arm_nandio.c
> +++ b/src/flash/arm_nandio.c
> @@ -138,7 +138,7 @@ int arm_nandwrite(struct arm_nand_data *nand, uint8_t
> *data, int size)
> /* set up algorithm and parameters */
> algo.common_magic = ARMV4_5_COMMON_MAGIC;
> algo.core_mode = ARMV4_5_MODE_SVC;
> - algo.core_state = ARMV4_5_STATE_ARM;
> + algo.core_state = ARM_STATE_ARM;
>
> init_reg_param(®_params[0], "r0", 32, PARAM_IN);
> init_reg_param(®_params[1], "r1", 32, PARAM_IN);
> @@ -214,7 +214,7 @@ int arm_nandread(struct arm_nand_data *nand, uint8_t
> *data, uint32_t size)
> /* set up algorithm and parameters */
> algo.common_magic = ARMV4_5_COMMON_MAGIC;
> algo.core_mode = ARMV4_5_MODE_SVC;
> - algo.core_state = ARMV4_5_STATE_ARM;
> + algo.core_state = ARM_STATE_ARM;
>
> init_reg_param(®_params[0], "r0", 32, PARAM_IN);
> init_reg_param(®_params[1], "r1", 32, PARAM_IN);
> --- a/src/flash/nor/aduc702x.c
> +++ b/src/flash/nor/aduc702x.c
> @@ -243,7 +243,7 @@ static int aduc702x_write_block(struct flash_bank *bank,
> uint8_t *buffer, uint32
>
> armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
> armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
> - armv4_5_info.core_state = ARMV4_5_STATE_ARM;
> + armv4_5_info.core_state = ARM_STATE_ARM;
>
> init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
> init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
> --- a/src/flash/nor/cfi.c
> +++ b/src/flash/nor/cfi.c
> @@ -1087,7 +1087,7 @@ static int cfi_intel_write_block(struct flash_bank
> *bank, uint8_t *buffer, uint3
>
> armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
> armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
> - armv4_5_info.core_state = ARMV4_5_STATE_ARM;
> + armv4_5_info.core_state = ARM_STATE_ARM;
>
> /* If we are setting up the write_algorith, we need target_code_src */
> /* if not we only need target_code_size. */
> @@ -1410,7 +1410,7 @@ static int cfi_spansion_write_block(struct flash_bank
> *bank, uint8_t *buffer, ui
>
> armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
> armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
> - armv4_5_info.core_state = ARMV4_5_STATE_ARM;
> + armv4_5_info.core_state = ARM_STATE_ARM;
>
> int target_code_size;
> const uint32_t *target_code_src;
> --- a/src/flash/nor/ecos.c
> +++ b/src/flash/nor/ecos.c
> @@ -212,7 +212,7 @@ static int runCode(struct ecosflash_flash_bank *info,
> struct armv4_5_algorithm armv4_5_info;
> armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
> armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
> - armv4_5_info.core_state = ARMV4_5_STATE_ARM;
> + armv4_5_info.core_state = ARM_STATE_ARM;
>
> init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT);
> init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
> --- a/src/flash/nor/lpc2000.c
> +++ b/src/flash/nor/lpc2000.c
> @@ -294,7 +294,7 @@ static int lpc2000_iap_call(struct flash_bank *bank, int
> code, uint32_t param_ta
> case lpc2000_v2:
> armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
> armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
> - armv4_5_info.core_state = ARMV4_5_STATE_ARM;
> + armv4_5_info.core_state = ARM_STATE_ARM;
> iap_entry_point = 0x7ffffff1;
> break;
> default:
> --- a/src/flash/nor/lpc2900.c
> +++ b/src/flash/nor/lpc2900.c
> @@ -1425,7 +1425,7 @@ static int lpc2900_write(struct flash_bank *bank,
> uint8_t *buffer,
> /* Execute algorithm, assume breakpoint for last
> instruction */
> armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
> armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
> - armv4_5_info.core_state = ARMV4_5_STATE_ARM;
> + armv4_5_info.core_state = ARM_STATE_ARM;
>
> retval = target_run_algorithm(target, 0, NULL, 5,
> reg_params,
> (warea->address) + buffer_size,
> --- a/src/flash/nor/str7x.c
> +++ b/src/flash/nor/str7x.c
> @@ -373,7 +373,7 @@ static int str7x_write_block(struct flash_bank *bank,
> uint8_t *buffer, uint32_t
>
> armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
> armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
> - armv4_5_info.core_state = ARMV4_5_STATE_ARM;
> + armv4_5_info.core_state = ARM_STATE_ARM;
>
> init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
> init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
> --- a/src/flash/nor/str9x.c
> +++ b/src/flash/nor/str9x.c
> @@ -410,7 +410,7 @@ static int str9x_write_block(struct flash_bank *bank,
>
> armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
> armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
> - armv4_5_info.core_state = ARMV4_5_STATE_ARM;
> + armv4_5_info.core_state = ARM_STATE_ARM;
>
> init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
> init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
> --- a/src/target/arm7_9_common.c
> +++ b/src/target/arm7_9_common.c
> @@ -1211,7 +1211,7 @@ int arm7_9_soft_reset_halt(struct target *target)
> uint32_t r0_thumb, pc_thumb;
> LOG_DEBUG("target entered debug from Thumb state, changing to
> ARM");
> /* Entered debug from Thumb mode */
> - armv4_5->core_state = ARMV4_5_STATE_THUMB;
> + armv4_5->core_state = ARM_STATE_THUMB;
> arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
> }
>
> @@ -1373,7 +1373,7 @@ static int arm7_9_debug_entry(struct target *target)
> {
> LOG_DEBUG("target entered debug from Thumb state");
> /* Entered debug from Thumb mode */
> - armv4_5->core_state = ARMV4_5_STATE_THUMB;
> + armv4_5->core_state = ARM_STATE_THUMB;
> cpsr_mask = 1 << 5;
> arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
> LOG_DEBUG("r0_thumb: 0x%8.8" PRIx32
> @@ -1385,13 +1385,13 @@ static int arm7_9_debug_entry(struct target *target)
> * B.7.3 for the reverse. That'd be the bare minimum...
> */
> LOG_DEBUG("target entered debug from Jazelle state");
> - armv4_5->core_state = ARMV4_5_STATE_JAZELLE;
> + armv4_5->core_state = ARM_STATE_JAZELLE;
> cpsr_mask = 1 << 24;
> LOG_ERROR("Jazelle debug entry -- BROKEN!");
> } else {
> LOG_DEBUG("target entered debug from ARM state");
> /* Entered debug from ARM mode */
> - armv4_5->core_state = ARMV4_5_STATE_ARM;
> + armv4_5->core_state = ARM_STATE_ARM;
> }
>
> for (i = 0; i < 16; i++)
> @@ -1419,21 +1419,21 @@ static int arm7_9_debug_entry(struct target *target)
> LOG_DEBUG("target entered debug state in %s mode",
> arm_mode_name(armv4_5->core_mode));
>
> - if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
> + if (armv4_5->core_state == ARM_STATE_THUMB)
> {
> LOG_DEBUG("thumb state, applying fixups");
> context[0] = r0_thumb;
> context[15] = pc_thumb;
> - } else if (armv4_5->core_state == ARMV4_5_STATE_ARM)
> + } else if (armv4_5->core_state == ARM_STATE_ARM)
> {
> /* adjust value stored by STM */
> context[15] -= 3 * 4;
> }
>
> if ((target->debug_reason != DBG_REASON_DBGRQ) || (!arm7_9->use_dbgrq))
> - context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM)
> ? 4 : 2);
> + context[15] -= 3 * ((armv4_5->core_state == ARM_STATE_ARM) ? 4
> : 2);
> else
> - context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state
> == ARMV4_5_STATE_ARM) ? 4 : 2);
> + context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state
> == ARM_STATE_ARM) ? 4 : 2);
>
> for (i = 0; i <= 15; i++)
> {
> @@ -1846,9 +1846,9 @@ int arm7_9_resume(struct target *target, int current,
> uint32_t address, int hand
> return retval;
> }
>
> - if (armv4_5->core_state == ARMV4_5_STATE_ARM)
> + if (armv4_5->core_state == ARM_STATE_ARM)
> arm7_9->branch_resume(target);
> - else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
> + else if (armv4_5->core_state == ARM_STATE_THUMB)
> {
> arm7_9->branch_resume_thumb(target);
> }
> @@ -1895,11 +1895,11 @@ int arm7_9_resume(struct target *target, int current,
> uint32_t address, int hand
> return retval;
> }
>
> - if (armv4_5->core_state == ARMV4_5_STATE_ARM)
> + if (armv4_5->core_state == ARM_STATE_ARM)
> {
> arm7_9->branch_resume(target);
> }
> - else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
> + else if (armv4_5->core_state == ARM_STATE_THUMB)
> {
> arm7_9->branch_resume_thumb(target);
> }
> @@ -2046,11 +2046,11 @@ int arm7_9_step(struct target *target, int current,
> uint32_t address, int handle
>
> arm7_9->enable_single_step(target, next_pc);
>
> - if (armv4_5->core_state == ARMV4_5_STATE_ARM)
> + if (armv4_5->core_state == ARM_STATE_ARM)
> {
> arm7_9->branch_resume(target);
> }
> - else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
> + else if (armv4_5->core_state == ARM_STATE_THUMB)
> {
> arm7_9->branch_resume_thumb(target);
> }
> @@ -2698,7 +2698,7 @@ int arm7_9_bulk_write_memory(struct target *target,
> uint32_t address, uint32_t c
>
> armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
> armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
> - armv4_5_info.core_state = ARMV4_5_STATE_ARM;
> + armv4_5_info.core_state = ARM_STATE_ARM;
>
> init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT);
>
> --- a/src/target/arm_dpm.c
> +++ b/src/target/arm_dpm.c
> @@ -147,14 +147,14 @@ static int dpm_read_reg(struct arm_dpm *dpm, struct reg
> *r, unsigned regnum)
> * is always right except in those broken-by-intent cases.
> */
> switch (dpm->arm->core_state) {
> - case ARMV4_5_STATE_ARM:
> + case ARM_STATE_ARM:
> value -= 8;
> break;
> - case ARMV4_5_STATE_THUMB:
> + case ARM_STATE_THUMB:
> case ARM_STATE_THUMB_EE:
> value -= 4;
> break;
> - case ARMV4_5_STATE_JAZELLE:
> + case ARM_STATE_JAZELLE:
> /* core-specific ... ? */
> LOG_WARNING("Jazelle PC adjustment unknown");
> break;
> @@ -744,14 +744,14 @@ static int dpm_remove_watchpoint(struct target *target,
> struct watchpoint *wp)
> void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t addr)
> {
> switch (dpm->arm->core_state) {
> - case ARMV4_5_STATE_ARM:
> + case ARM_STATE_ARM:
> addr -= 8;
> break;
> - case ARMV4_5_STATE_THUMB:
> + case ARM_STATE_THUMB:
> case ARM_STATE_THUMB_EE:
> addr -= 4;
> break;
> - case ARMV4_5_STATE_JAZELLE:
> + case ARM_STATE_JAZELLE:
> /* ?? */
> break;
> }
> --- a/src/target/arm_semihosting.c
> +++ b/src/target/arm_semihosting.c
> @@ -387,7 +387,7 @@ static int do_semihosting(struct target *target)
> armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
> armv4_5->core_mode = spsr & 0x1f;
> if (spsr & 0x20)
> - armv4_5->core_state = ARMV4_5_STATE_THUMB;
> + armv4_5->core_state = ARM_STATE_THUMB;
> return target_resume(target, 1, 0, 0, 0);
> }
>
> --- a/src/target/arm_simulator.c
> +++ b/src/target/arm_simulator.c
> @@ -135,7 +135,7 @@ static uint32_t arm_shifter_operand(struct
> arm_sim_interface *sim,
> uint32_t return_value;
> int instruction_size;
>
> - if (sim->get_state(sim) == ARMV4_5_STATE_ARM)
> + if (sim->get_state(sim) == ARM_STATE_ARM)
> instruction_size = 4;
> else
> instruction_size = 2;
> @@ -286,7 +286,7 @@ int arm_simulate_step_core(struct target *target,
> int instruction_size;
> int retval = ERROR_OK;
>
> - if (sim->get_state(sim) == ARMV4_5_STATE_ARM)
> + if (sim->get_state(sim) == ARM_STATE_ARM)
> {
> uint32_t opcode;
>
> @@ -392,7 +392,7 @@ int arm_simulate_step_core(struct target *target,
> else if (instruction.type == ARM_BL)
> {
> uint32_t old_pc = sim->get_reg(sim, 15);
> - int T = (sim->get_state(sim) ==
> ARMV4_5_STATE_THUMB);
> + int T = (sim->get_state(sim) ==
> ARM_STATE_THUMB);
> sim->set_reg_mode(sim, 14, old_pc + 4 + T);
> sim->set_reg(sim, 15, target);
> }
> @@ -400,27 +400,27 @@ int arm_simulate_step_core(struct target *target,
> {
> if (target & 0x1)
> {
> - sim->set_state(sim,
> ARMV4_5_STATE_THUMB);
> + sim->set_state(sim, ARM_STATE_THUMB);
> }
> else
> {
> - sim->set_state(sim, ARMV4_5_STATE_ARM);
> + sim->set_state(sim, ARM_STATE_ARM);
> }
> sim->set_reg(sim, 15, target & 0xfffffffe);
> }
> else if (instruction.type == ARM_BLX)
> {
> uint32_t old_pc = sim->get_reg(sim, 15);
> - int T = (sim->get_state(sim) ==
> ARMV4_5_STATE_THUMB);
> + int T = (sim->get_state(sim) ==
> ARM_STATE_THUMB);
> sim->set_reg_mode(sim, 14, old_pc + 4 + T);
>
> if (target & 0x1)
> {
> - sim->set_state(sim,
> ARMV4_5_STATE_THUMB);
> + sim->set_state(sim, ARM_STATE_THUMB);
> }
> else
> {
> - sim->set_state(sim, ARMV4_5_STATE_ARM);
> + sim->set_state(sim, ARM_STATE_ARM);
> }
> sim->set_reg(sim, 15, target & 0xfffffffe);
> }
> @@ -493,9 +493,9 @@ int arm_simulate_step_core(struct target *target,
> if (instruction.info.data_proc.Rd == 15) {
> sim->set_reg_mode(sim, 15, Rd & ~1);
> if (Rd & 1)
> - sim->set_state(sim,
> ARMV4_5_STATE_THUMB);
> + sim->set_state(sim, ARM_STATE_THUMB);
> else
> - sim->set_state(sim, ARMV4_5_STATE_ARM);
> + sim->set_state(sim, ARM_STATE_ARM);
> return ERROR_OK;
> }
> sim->set_reg_mode(sim, instruction.info.data_proc.Rd,
> Rd);
> @@ -605,9 +605,9 @@ int arm_simulate_step_core(struct target *target,
> if (instruction.info.load_store.Rd == 15) {
> sim->set_reg_mode(sim, 15, load_value & ~1);
> if (load_value & 1)
> - sim->set_state(sim,
> ARMV4_5_STATE_THUMB);
> + sim->set_state(sim, ARM_STATE_THUMB);
> else
> - sim->set_state(sim, ARMV4_5_STATE_ARM);
> + sim->set_state(sim, ARM_STATE_ARM);
> return ERROR_OK;
> }
> sim->set_reg_mode(sim, instruction.info.load_store.Rd,
> load_value);
> @@ -684,9 +684,9 @@ int arm_simulate_step_core(struct target *target,
> uint32_t val = load_values[i];
> sim->set_reg_mode(sim, i, val & ~1);
> if (val & 1)
> - sim->set_state(sim,
> ARMV4_5_STATE_THUMB);
> + sim->set_state(sim,
> ARM_STATE_THUMB);
> else
> - sim->set_state(sim,
> ARMV4_5_STATE_ARM);
> + sim->set_state(sim,
> ARM_STATE_ARM);
> } else {
> sim->set_reg_mode(sim, i,
> load_values[i]);
> }
> --- a/src/target/armv4_5.c
> +++ b/src/target/armv4_5.c
> @@ -381,13 +381,13 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
> LOG_WARNING("ThumbEE -- incomplete support");
> state = ARM_STATE_THUMB_EE;
> } else
> - state = ARMV4_5_STATE_THUMB;
> + state = ARM_STATE_THUMB;
> } else {
> if (cpsr & (1 << 24)) { /* J */
> LOG_ERROR("Jazelle state handling is BROKEN!");
> - state = ARMV4_5_STATE_JAZELLE;
> + state = ARM_STATE_JAZELLE;
> } else
> - state = ARMV4_5_STATE_ARM;
> + state = ARM_STATE_ARM;
> }
> arm->core_state = state;
>
> @@ -710,11 +710,11 @@ COMMAND_HANDLER(handle_armv4_5_core_state_command)
> {
> if (strcmp(CMD_ARGV[0], "arm") == 0)
> {
> - armv4_5->core_state = ARMV4_5_STATE_ARM;
> + armv4_5->core_state = ARM_STATE_ARM;
> }
> if (strcmp(CMD_ARGV[0], "thumb") == 0)
> {
> - armv4_5->core_state = ARMV4_5_STATE_THUMB;
> + armv4_5->core_state = ARM_STATE_THUMB;
> }
> }
>
> @@ -1115,9 +1115,9 @@ int armv4_5_run_algorithm_inner(struct target *target,
> }
>
> armv4_5->core_state = armv4_5_algorithm_info->core_state;
> - if (armv4_5->core_state == ARMV4_5_STATE_ARM)
> + if (armv4_5->core_state == ARM_STATE_ARM)
> exit_breakpoint_size = 4;
> - else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
> + else if (armv4_5->core_state == ARM_STATE_THUMB)
> exit_breakpoint_size = 2;
> else
> {
> @@ -1275,7 +1275,7 @@ int arm_checksum_memory(struct target *target,
>
> armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
> armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
> - armv4_5_info.core_state = ARMV4_5_STATE_ARM;
> + armv4_5_info.core_state = ARM_STATE_ARM;
>
> init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT);
> init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
> @@ -1352,7 +1352,7 @@ int arm_blank_check_memory(struct target *target,
>
> armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
> armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
> - armv4_5_info.core_state = ARMV4_5_STATE_ARM;
> + armv4_5_info.core_state = ARM_STATE_ARM;
>
> init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
> buf_set_u32(reg_params[0].value, 0, 32, address);
> --- a/src/target/armv4_5.h
> +++ b/src/target/armv4_5.h
> @@ -51,9 +51,9 @@ enum armv4_5_mode armv4_5_number_to_mode(int number);
>
> typedef enum armv4_5_state
> {
> - ARMV4_5_STATE_ARM,
> - ARMV4_5_STATE_THUMB,
> - ARMV4_5_STATE_JAZELLE,
> + ARM_STATE_ARM,
> + ARM_STATE_THUMB,
> + ARM_STATE_JAZELLE,
> ARM_STATE_THUMB_EE,
> } armv4_5_state_t;
>
> --- a/src/target/cortex_a8.c
> +++ b/src/target/cortex_a8.c
> @@ -705,17 +705,17 @@ static int cortex_a8_resume(struct target *target, int
> current,
> */
> switch (armv4_5->core_state)
> {
> - case ARMV4_5_STATE_ARM:
> + case ARM_STATE_ARM:
> resume_pc &= 0xFFFFFFFC;
> break;
> - case ARMV4_5_STATE_THUMB:
> + case ARM_STATE_THUMB:
> case ARM_STATE_THUMB_EE:
> /* When the return address is loaded into PC
> * bit 0 must be 1 to stay in Thumb state
> */
> resume_pc |= 0x1;
> break;
> - case ARMV4_5_STATE_JAZELLE:
> + case ARM_STATE_JAZELLE:
> LOG_ERROR("How do I resume into Jazelle state??");
> return ERROR_FAIL;
> }
> @@ -974,7 +974,7 @@ static int cortex_a8_step(struct target *target, int
> current, uint32_t address,
>
> /* Setup single step breakpoint */
> stepbreakpoint.address = address;
> - stepbreakpoint.length = (armv4_5->core_state == ARMV4_5_STATE_THUMB)
> + stepbreakpoint.length = (armv4_5->core_state == ARM_STATE_THUMB)
> ? 2 : 4;
> stepbreakpoint.type = BKPT_HARD;
> stepbreakpoint.set = 0;
> --- a/src/target/etm.c
> +++ b/src/target/etm.c
> @@ -659,7 +659,7 @@ static int etm_read_instruction(struct etm_context *ctx,
> struct arm_instruction
> return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
> }
>
> - if (ctx->core_state == ARMV4_5_STATE_ARM)
> + if (ctx->core_state == ARM_STATE_ARM)
> {
> uint8_t buf[4];
> if ((retval = image_read_section(ctx->image, section,
> @@ -672,7 +672,7 @@ static int etm_read_instruction(struct etm_context *ctx,
> struct arm_instruction
> opcode = target_buffer_get_u32(ctx->target, buf);
> arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
> }
> - else if (ctx->core_state == ARMV4_5_STATE_THUMB)
> + else if (ctx->core_state == ARM_STATE_THUMB)
> {
> uint8_t buf[2];
> if ((retval = image_read_section(ctx->image, section,
> @@ -685,7 +685,7 @@ static int etm_read_instruction(struct etm_context *ctx,
> struct arm_instruction
> opcode = target_buffer_get_u16(ctx->target, buf);
> thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
> }
> - else if (ctx->core_state == ARMV4_5_STATE_JAZELLE)
> + else if (ctx->core_state == ARM_STATE_JAZELLE)
> {
> LOG_ERROR("BUG: tracing of jazelle code not supported");
> return ERROR_FAIL;
> @@ -829,7 +829,7 @@ static int etmv1_branch_address(struct etm_context *ctx)
> /* if a full address was output, we might have branched into Jazelle
> state */
> if ((shift == 32) && (packet & 0x80))
> {
> - ctx->core_state = ARMV4_5_STATE_JAZELLE;
> + ctx->core_state = ARM_STATE_JAZELLE;
> }
> else
> {
> @@ -837,12 +837,12 @@ static int etmv1_branch_address(struct etm_context *ctx)
> * encoded in bit 0 of the branch target address */
> if (ctx->last_branch & 0x1)
> {
> - ctx->core_state = ARMV4_5_STATE_THUMB;
> + ctx->core_state = ARM_STATE_THUMB;
> ctx->last_branch &= ~0x1;
> }
> else
> {
> - ctx->core_state = ARMV4_5_STATE_ARM;
> + ctx->core_state = ARM_STATE_ARM;
> ctx->last_branch &= ~0x3;
> }
> }
> @@ -1126,12 +1126,12 @@ static int etmv1_analyze_trace(struct etm_context
> *ctx, struct command_context *
> }
> else
> {
> - next_pc += (ctx->core_state ==
> ARMV4_5_STATE_ARM) ? 4 : 2;
> + next_pc += (ctx->core_state == ARM_STATE_ARM) ?
> 4 : 2;
> }
> }
> else if (pipestat == STAT_IN)
> {
> - next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 :
> 2;
> + next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2;
> }
>
> if ((pipestat != STAT_TD) && (pipestat != STAT_WT))
> @@ -1498,7 +1498,7 @@ COMMAND_HANDLER(handle_etm_config_command)
> etm_ctx->trigger_percent = 50;
> etm_ctx->trace_data = NULL;
> etm_ctx->portmode = portmode;
> - etm_ctx->core_state = ARMV4_5_STATE_ARM;
> + etm_ctx->core_state = ARM_STATE_ARM;
>
> arm->etm = etm_ctx;
>
> --- a/src/target/feroceon.c
> +++ b/src/target/feroceon.c
> @@ -524,7 +524,7 @@ int feroceon_bulk_write_memory(struct target *target,
> uint32_t address, uint32_t
> buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address);
> armv4_5->core_cache->reg_list[0].valid = 1;
> armv4_5->core_cache->reg_list[0].dirty = 1;
> - armv4_5->core_state = ARMV4_5_STATE_ARM;
> + armv4_5->core_state = ARM_STATE_ARM;
>
> embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA],
> 0);
> arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
> --- a/src/target/xscale.c
> +++ b/src/target/xscale.c
> @@ -2607,7 +2607,7 @@ static int xscale_read_instruction(struct target
> *target,
> return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
> }
>
> - if (xscale->trace.core_state == ARMV4_5_STATE_ARM)
> + if (xscale->trace.core_state == ARM_STATE_ARM)
> {
> uint8_t buf[4];
> if ((retval = image_read_section(xscale->trace.image, section,
> @@ -2620,7 +2620,7 @@ static int xscale_read_instruction(struct target
> *target,
> opcode = target_buffer_get_u32(target, buf);
> arm_evaluate_opcode(opcode, xscale->trace.current_pc,
> instruction);
> }
> - else if (xscale->trace.core_state == ARMV4_5_STATE_THUMB)
> + else if (xscale->trace.core_state == ARM_STATE_THUMB)
> {
> uint8_t buf[2];
> if ((retval = image_read_section(xscale->trace.image, section,
> @@ -2672,7 +2672,7 @@ static int xscale_analyze_trace(struct target *target,
> struct command_context *c
> int rollover;
> int branch;
> int exception;
> - xscale->trace.core_state = ARMV4_5_STATE_ARM;
> + xscale->trace.core_state = ARM_STATE_ARM;
>
> chkpt = 0;
> rollover = 0;
> @@ -2806,7 +2806,7 @@ static int xscale_analyze_trace(struct target *target,
> struct command_context *c
> }
> else
> {
> - xscale->trace.current_pc +=
> (xscale->trace.core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
> + xscale->trace.current_pc +=
> (xscale->trace.core_state == ARM_STATE_ARM) ? 4 : 2;
> }
> command_print(cmd_ctx, "%s",
> instruction.text);
> }
> @@ -2821,7 +2821,7 @@ static int xscale_analyze_trace(struct target *target,
> struct command_context *c
> }
> }
>
> - for (; xscale->trace.current_pc < trace_data->last_instruction;
> xscale->trace.current_pc += (xscale->trace.core_state == ARMV4_5_STATE_ARM) ?
> 4 : 2)
> + for (; xscale->trace.current_pc < trace_data->last_instruction;
> xscale->trace.current_pc += (xscale->trace.core_state == ARM_STATE_ARM) ? 4 :
> 2)
> {
> struct arm_instruction instruction;
> if ((retval = xscale_read_instruction(target,
> &instruction)) != ERROR_OK)
> _______________________________________________
> Openocd-development mailing list
> [email protected]
> https://lists.berlios.de/mailman/listinfo/openocd-development
_______________________________________________
Openocd-development mailing list
[email protected]
https://lists.berlios.de/mailman/listinfo/openocd-development
