On Tuesday 15 December 2009, Dean Glazeski wrote:
> I noticed the NAND erase function was doing page command stuff, so I pulled
> the redundant code out.  Patch is attached

This doesn't look right.  Consider the 16 Gbit large page chip
I happen to have on some boards here:

 - read/write of 2KB page uses 5 byte addressing
 - erase of 128KB block uses 3 byte addressping

You're making both use the 5 byte addressing ... basically, if
this is going to be shared, the erase commands shouldn't be
writing column addresses, just row addresses.

- Dave



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