Command "reset halt" checks if PC properly resets, issueing warning: "PC was not 0. Does this target need srst_pulls_trst?". Checking PC against 0 is not always correct.
ARM cores have HW signal VINITHI to force exception vectors at high addresses. If at reset VINITHI is high, it sets "V" bit in Control Register c1 and forces address 0xffff0000 as next PC. Signed-off-by: Antonio Borneo <[email protected]> --- src/target/arm7_9_common.c | 14 ++++++++++++-- 1 files changed, 12 insertions(+), 2 deletions(-) diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index 280704e..5154a5d 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -911,9 +911,19 @@ int arm7_9_poll(struct target *target) { struct reg *reg = register_get_by_name(target->reg_cache, "pc", 1); uint32_t t=*((uint32_t *)reg->value); - if (t != 0) + uint32_t v=0, pc; + /* Get location of exception vectors (C1 bit 13) */ + if (!arm7_9->armv4_5_common.mrc) { - LOG_ERROR("PC was not 0. Does this target need srst_pulls_trst?"); + LOG_ERROR("Ooops! Missing armv4_5_common.mrc"); + return ERROR_FAIL; + } + if ((retval = (*arm7_9->armv4_5_common.mrc)(target, 15, 0, 0, 1, 0, &v)) != ERROR_OK) + return retval; + pc = (v & 0x00002000) ? 0xffff0000 : 0; + if (t != pc) + { + LOG_ERROR("PC was not 0x%x. Does this target need srst_pulls_trst?", pc); } } -- 1.6.5.2 _______________________________________________ Openocd-development mailing list [email protected] https://lists.berlios.de/mailman/listinfo/openocd-development
