On 17.12.2009 19:39, David Brownell wrote:
> On Thursday 17 December 2009, Dirk Behme wrote:
>
>> Ok, after board reset I get
>>
>> -- cut --
>> > scan_chain
>> TapName Enabled IdCode Expected IrLen IrCap IrMask
>> -- ------------------- -------- ---------- ---------- ----- ----- ------
>> 0 omap3530.dsp n 0x00000000 0x00000000 38 0x25 0x3f
>> 1 omap3530.dap Y 0x00000000 0x0b6d602f 4 0x01 0x0f
>> 2 omap3530.jrc Y 0x0b7ae02f 0x0b7ae02f 6 0x01 0x3f
>> -- cut --
>>
>> *without* manually calling omap3_dbginit. Most probably this is the
>> expected behavior? Looking at the scripts, omap3_dbginit seems to be
>> called automatically, now?
>
> Yes. And my notes suggest that it shouldn't need to be exposed
> via Tcl scripting either ... are its guts not called automagically
> when the target.examine() method is called? That must be called
> before *ANYTHING* can be done with the target. QED ... but I did
> not chase it down.
>
> I was kind of focussing on getting ICEpick integration to behave
> sanely, when I did that, not specifically on OMAP3. So now we
> have ICEpick behaving the same way on Davinci and OMAP3 -- the ARM
> is automatically added to the scan chain after reset, and maybe
> the ETB too (on DaVinci) -- suggesting that the OpenOCD event
> infrastructure and TAP activation logic is doing relatively sane
> things. That didn't especially involve A8 updates though.
>
> (And similarly with the DPM, register, and watchpoint updates:
> my focus was shared infrastructure. In that case however the
> A8 updates added missing capabilities to A8 support.)
>
>
>> But, after reset, OpenOCD start reports a lot of STICKY ERRORs:
>>
>> -- cut --
>> # ./bin/openocd -s lib/openocd/ -f interface/flyswatter.cfg -f
>> board/ti_beagleboard.cfg
>>
>> Open On-Chip Debugger 0.4.0-dev-00955-g3616b93 (2009-12-17-17:30)
>>
>> For bug reports, read
>>
>> http://openocd.berlios.de/doc/doxygen/bugs.html
>>
>> RCLK - adaptive
>>
>> Warn : omap3530.dsp: huge IR length 38
>> RCLK - adaptive
>> trst_only separate trst_push_pull
>> Info : RCLK (adaptive clock speed) not supported - fallback to 1000 kHz
>> Info : JTAG tap: omap3530.jrc tap/device found: 0x0b7ae02f (mfg:
>> 0x017, part: 0xb7ae, ver: 0x0)
>> Info : JTAG tap: omap3530.dap enabled
>> Info : omap3530.cpu: hardware has 6 breakpoints, 2 watchpoints
>> Error: AHBAP Cached values: dp_select 0x10, ap_csw 0xa2000002, ap_tar
>> 0x54011140
>> Error: SWJ-DP STICKY ERROR
>> Error: Read MEM_AP_CSW 0x2800042, MEM_AP_TAR 0x54011140
>> Error: AHBAP Cached values: dp_select 0x10, ap_csw 0xa2000002, ap_tar
>> 0x54011140
>> Error: SWJ-DP STICKY ERROR
>> Error: Read MEM_AP_CSW 0x2800042, MEM_AP_TAR 0x54011140
>> Error: AHBAP Cached values: dp_select 0x10, ap_csw 0xa2000002, ap_tar
>> 0x54011140
>> Error: SWJ-DP STICKY ERROR
>> Error: Read MEM_AP_CSW 0x2800042, MEM_AP_TAR 0x54011140
>> Error: AHBAP Cached values: dp_select 0x10, ap_csw 0xa2000002, ap_tar
>> 0x54011140
>> Error: SWJ-DP STICKY ERROR
>> Error: Read MEM_AP_CSW 0x2800042, MEM_AP_TAR 0x54011140
>> Error: AHBAP Cached values: dp_select 0x10, ap_csw 0xa2000002, ap_tar
>> 0x54011150
>> Error: SWJ-DP STICKY ERROR
>> Error: Read MEM_AP_CSW 0x2800042, MEM_AP_TAR 0x54011150
>> Error: AHBAP Cached values: dp_select 0x10, ap_csw 0xa2000002, ap_tar
>> 0x54011150
>> Error: SWJ-DP STICKY ERROR
>> Error: Read MEM_AP_CSW 0x2800042, MEM_AP_TAR 0x54011150
>> Error: AHBAP Cached values: dp_select 0x10, ap_csw 0xa2000002, ap_tar
>> 0x540111c0
>> Error: SWJ-DP STICKY ERROR
>> Error: Read MEM_AP_CSW 0x2800042, MEM_AP_TAR 0x540111c0
>> Error: AHBAP Cached values: dp_select 0x10, ap_csw 0xa2000002, ap_tar
>> 0x540111c0
>> Error: SWJ-DP STICKY ERROR
>> Error: Read MEM_AP_CSW 0x2800042, MEM_AP_TAR 0x540111c0
>> -- cut --
>>
>> Is this expected?
>
> I don't recall seeing that, no. Are "sticky" errors cleared
> correctly? ISTR thinking for some reason they weren't ...
>
> What was it trying to access when it got those errors?
>
> It shouldn't matter ... but I'm using a rev B5 Beagle, which
> means not-the-latest-Cortex. R2P1 or somesuch not R3Px.
I did some additional tests:
* I updated to 0.4.0-rc1-dev-00001-g4e2b15f (2009-12-23-08:09)
* I have Beagle A4 and C1.
* Both show above sticky errors after board "cold" start. I.e. power
up the board, let it wait at U-Boot prompt and then start
openocd -s lib/openocd/ -f interface/flyswatter.cfg -f
board/ti_beagleboard.cfg
will result in above sticky errors.
* With a OpenOCD "warm" re-start (i.e. don't touch Beagle power, just
exit OpenOCD and restart it) I don't get above sticky errors. Instead
I get
-- cut --
...
RCLK - adaptive
Warn : omap3530.dsp: huge IR length 38
RCLK - adaptive
trst_only separate trst_push_pull
Info : RCLK (adaptive clock speed) not supported - fallback to 1000 kHz
Info : TAP omap3530.jrc does not have IDCODE
Warn : JTAG tap: omap3530.jrc UNEXPECTED: 0x00000000 (mfg:
0x000, part: 0x0000, ver: 0x0)
Error: JTAG tap: omap3530.jrc expected 1 of 1: 0x0b7ae02f (mfg:
0x017, part: 0xb7ae, ver: 0x0)
Error: Trying to use configured scan chain anyway...
Warn : Bypassing JTAG setup events due to errors
-- cut --
which can be "fixed" by manual 'reset halt':
-- cut --
> telnet localhost 4444
Trying 127.0.0.1...
Connected to localhost.
Escape character is '^]'.
Open On-Chip Debugger
> scan_chain
TapName Enabled IdCode Expected IrLen IrCap IrMask
-- ------------------- -------- ---------- ---------- ----- ----- ------
0 omap3530.dsp n 0x00000000 0x00000000 38 0x25 0x3f
1 omap3530.dap n 0x00000000 0x0b6d602f 4 0x01 0x0f
2 omap3530.jrc Y 0x00000000 0x0b7ae02f 6 0x01 0x3f
> reset halt
RCLK not supported - fallback to 1000 kHz
JTAG tap: omap3530.jrc tap/device found: 0x0b7ae02f (mfg: 0x017, part:
0xb7ae, ver: 0x0)
JTAG tap: omap3530.dap enabled
omap3530.cpu: hardware has 6 breakpoints, 2 watchpoints
omap3530.cpu: ran after reset and before halt ...
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x600001d3 pc: 0x402025cc
MMU: disabled, D-Cache: disabled, I-Cache: enabled
> scan_chain
TapName Enabled IdCode Expected IrLen IrCap IrMask
-- ------------------- -------- ---------- ---------- ----- ----- ------
0 omap3530.dsp n 0x00000000 0x00000000 38 0x25 0x3f
1 omap3530.dap Y 0x00000000 0x0b6d602f 4 0x01 0x0f
2 omap3530.jrc Y 0x0b7ae02f 0x0b7ae02f 6 0x01 0x3f
>
-- cut --
* Regarding above question "What was it trying to access when it got
those [sticky] errors?" I enabled --debug and got stuff below [1].
Does this help?
Best regards
Dirk
[1] Output of
openocd -s lib/openocd/ -f interface/flyswatter.cfg -f
board/ti_beagleboard.cfg --debug
regarding sticky errors reported above:
...
Debug: 578 133 arm_adi_v5.c:960 ahbap_debugport_init():
Debug: 579 141 arm_adi_v5.c:1005 ahbap_debugport_init(): AHB-AP ID
Register 0x14770001, Debug ROM Address 0xffffffff
Debug: 580 156 cortex_a8.c:1502 cortex_a8_examine_first(): cpuid =
0x411fc082
Debug: 581 156 cortex_a8.c:1503 cortex_a8_examine_first(): ctypr =
0x80048004
Debug: 582 156 cortex_a8.c:1504 cortex_a8_examine_first(): ttypr =
0x00202001
Debug: 583 156 cortex_a8.c:1505 cortex_a8_examine_first(): didr =
0x15141012
Info : 584 156 arm_dpm.c:874 arm_dpm_setup(): omap3530.cpu: hardware
has 6 breakpoints, 2 watchpoints
Debug: 585 156 cortex_a8.c:518 cortex_a8_bpwp_disable(): A8: bpwp
disable, cr 54011140
Debug: 586 158 arm_adi_v5.c:243 swjdp_transaction_endcheck(): swjdp:
CTRL/STAT error 0xf0000021
Error: 587 158 arm_adi_v5.c:254 swjdp_transaction_endcheck(): AHBAP
Cached values: dp_select 0x10, ap_csw 0xa2000002, ap_tar 0x54011140
Error: 588 158 arm_adi_v5.c:259 swjdp_transaction_endcheck(): SWJ-DP
STICKY ERROR
Debug: 589 160 arm_adi_v5.c:267 swjdp_transaction_endcheck(): swjdp:
status 0xf0000001
Error: 590 161 arm_adi_v5.c:273 swjdp_transaction_endcheck(): Read
MEM_AP_CSW 0x2800042, MEM_AP_TAR 0x54011140
Debug: 591 161 cortex_a8.c:518 cortex_a8_bpwp_disable(): A8: bpwp
disable, cr 54011144
Debug: 592 163 arm_adi_v5.c:243 swjdp_transaction_endcheck(): swjdp:
CTRL/STAT error 0xf0000021
Error: 593 163 arm_adi_v5.c:254 swjdp_transaction_endcheck(): AHBAP
Cached values: dp_select 0x10, ap_csw 0xa2000002, ap_tar 0x54011140
Error: 594 163 arm_adi_v5.c:259 swjdp_transaction_endcheck(): SWJ-DP
STICKY ERROR
Debug: 595 168 arm_adi_v5.c:267 swjdp_transaction_endcheck(): swjdp:
status 0xf0000001
Error: 596 169 arm_adi_v5.c:273 swjdp_transaction_endcheck(): Read
MEM_AP_CSW 0x2800042, MEM_AP_TAR 0x54011140
Debug: 597 169 cortex_a8.c:518 cortex_a8_bpwp_disable(): A8: bpwp
disable, cr 54011148
Debug: 598 171 arm_adi_v5.c:243 swjdp_transaction_endcheck(): swjdp:
CTRL/STAT error 0xf0000021
Error: 599 171 arm_adi_v5.c:254 swjdp_transaction_endcheck(): AHBAP
Cached values: dp_select 0x10, ap_csw 0xa2000002, ap_tar 0x54011140
Error: 600 171 arm_adi_v5.c:259 swjdp_transaction_endcheck(): SWJ-DP
STICKY ERROR
Debug: 601 177 arm_adi_v5.c:267 swjdp_transaction_endcheck(): swjdp:
status 0xf0000001
Error: 602 179 arm_adi_v5.c:273 swjdp_transaction_endcheck(): Read
MEM_AP_CSW 0x2800042, MEM_AP_TAR 0x54011140
Debug: 603 179 cortex_a8.c:518 cortex_a8_bpwp_disable(): A8: bpwp
disable, cr 5401114c
Debug: 604 184 arm_adi_v5.c:243 swjdp_transaction_endcheck(): swjdp:
CTRL/STAT error 0xf0000021
Error: 605 184 arm_adi_v5.c:254 swjdp_transaction_endcheck(): AHBAP
Cached values: dp_select 0x10, ap_csw 0xa2000002, ap_tar 0x54011140
Error: 606 184 arm_adi_v5.c:259 swjdp_transaction_endcheck(): SWJ-DP
STICKY ERROR
Debug: 607 185 arm_adi_v5.c:267 swjdp_transaction_endcheck(): swjdp:
status 0xf0000001
Error: 608 187 arm_adi_v5.c:273 swjdp_transaction_endcheck(): Read
MEM_AP_CSW 0x2800042, MEM_AP_TAR 0x54011140
Debug: 609 187 cortex_a8.c:518 cortex_a8_bpwp_disable(): A8: bpwp
disable, cr 54011150
Debug: 610 192 arm_adi_v5.c:243 swjdp_transaction_endcheck(): swjdp:
CTRL/STAT error 0xf0000021
Error: 611 192 arm_adi_v5.c:254 swjdp_transaction_endcheck(): AHBAP
Cached values: dp_select 0x10, ap_csw 0xa2000002, ap_tar 0x54011150
Error: 612 192 arm_adi_v5.c:259 swjdp_transaction_endcheck(): SWJ-DP
STICKY ERROR
Debug: 613 193 arm_adi_v5.c:267 swjdp_transaction_endcheck(): swjdp:
status 0xf0000001
Error: 614 195 arm_adi_v5.c:273 swjdp_transaction_endcheck(): Read
MEM_AP_CSW 0x2800042, MEM_AP_TAR 0x54011150
Debug: 615 195 cortex_a8.c:518 cortex_a8_bpwp_disable(): A8: bpwp
disable, cr 54011154
Debug: 616 200 arm_adi_v5.c:243 swjdp_transaction_endcheck(): swjdp:
CTRL/STAT error 0xf0000021
Error: 617 200 arm_adi_v5.c:254 swjdp_transaction_endcheck(): AHBAP
Cached values: dp_select 0x10, ap_csw 0xa2000002, ap_tar 0x54011150
Error: 618 200 arm_adi_v5.c:259 swjdp_transaction_endcheck(): SWJ-DP
STICKY ERROR
Debug: 619 201 arm_adi_v5.c:267 swjdp_transaction_endcheck(): swjdp:
status 0xf0000001
Error: 620 203 arm_adi_v5.c:273 swjdp_transaction_endcheck(): Read
MEM_AP_CSW 0x2800042, MEM_AP_TAR 0x54011150
Debug: 621 203 cortex_a8.c:518 cortex_a8_bpwp_disable(): A8: bpwp
disable, cr 540111c0
Debug: 622 234 arm_adi_v5.c:243 swjdp_transaction_endcheck(): swjdp:
CTRL/STAT error 0xf0000021
Error: 623 234 arm_adi_v5.c:254 swjdp_transaction_endcheck(): AHBAP
Cached values: dp_select 0x10, ap_csw 0xa2000002, ap_tar 0x540111c0
Error: 624 234 arm_adi_v5.c:259 swjdp_transaction_endcheck(): SWJ-DP
STICKY ERROR
Debug: 625 240 arm_adi_v5.c:267 swjdp_transaction_endcheck(): swjdp:
status 0xf0000001
Error: 626 242 arm_adi_v5.c:273 swjdp_transaction_endcheck(): Read
MEM_AP_CSW 0x2800042, MEM_AP_TAR 0x540111c0
Debug: 627 242 cortex_a8.c:518 cortex_a8_bpwp_disable(): A8: bpwp
disable, cr 540111c4
Debug: 628 248 arm_adi_v5.c:243 swjdp_transaction_endcheck(): swjdp:
CTRL/STAT error 0xf0000021
Error: 629 248 arm_adi_v5.c:254 swjdp_transaction_endcheck(): AHBAP
Cached values: dp_select 0x10, ap_csw 0xa2000002, ap_tar 0x540111c0
Error: 630 248 arm_adi_v5.c:259 swjdp_transaction_endcheck(): SWJ-DP
STICKY ERROR
Debug: 631 248 arm_adi_v5.c:267 swjdp_transaction_endcheck(): swjdp:
status 0xf0000001
Error: 632 250 arm_adi_v5.c:273 swjdp_transaction_endcheck(): Read
MEM_AP_CSW 0x2800042, MEM_AP_TAR 0x540111c0
Debug: 633 250 cortex_a8.c:1528 cortex_a8_examine_first(): Configured
6 hw breakpoints
Debug: 634 250 cortex_a8.c:73 cortex_a8_init_debug_access():
Debug: 635 262 command.c:114 script_debug(): command - ocd_command
...
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