diff -crN openocdp1/openocd/src/flash/nand/lpc3180.c openocdp2/openocd/src/flash/nand/lpc3180.c *** openocdp1/openocd/src/flash/nand/lpc3180.c 2009-12-21 23:45:52.000000000 +0100 --- openocdp2/openocd/src/flash/nand/lpc3180.c 2010-01-10 16:24:23.000000000 +0100 *************** *** 500,508 **** return ERROR_NAND_OPERATION_NOT_SUPPORTED; } ! if (oob && (oob_size > 6)) { ! LOG_ERROR("LPC3180 MLC controller can't write more than 6 bytes of OOB data"); return ERROR_NAND_OPERATION_NOT_SUPPORTED; } --- 500,508 ---- return ERROR_NAND_OPERATION_NOT_SUPPORTED; } ! if (oob && (oob_size > 24)) { ! LOG_ERROR("LPC3180 MLC controller can't write more than 6 bytes for each quarters of OOB data"); return ERROR_NAND_OPERATION_NOT_SUPPORTED; } *************** *** 559,568 **** data += thisrun_data_size; } ! memset(oob_buffer, 0xff, (nand->page_size == 512) ? 6 : 24); if (oob) { ! memcpy(page_buffer, oob, thisrun_oob_size); oob_size -= thisrun_oob_size; oob += thisrun_oob_size; } --- 559,568 ---- data += thisrun_data_size; } ! memset(oob_buffer, 0xff, 6 ); if (oob) { ! memcpy(oob_buffer, oob, thisrun_oob_size); oob_size -= thisrun_oob_size; oob += thisrun_oob_size; } *************** *** 570,577 **** /* write MLC_ECC_ENC_REG to start encode cycle */ target_write_u32(target, 0x200b8008, 0x0); ! target_write_memory(target, 0x200a8000, 4, 128, page_buffer + (quarter * 512)); ! target_write_memory(target, 0x200a8000, 1, 6, oob_buffer + (quarter * 6)); /* write MLC_ECC_AUTO_ENC_REG to start auto encode */ target_write_u32(target, 0x200b8010, 0x0); --- 570,577 ---- /* write MLC_ECC_ENC_REG to start encode cycle */ target_write_u32(target, 0x200b8008, 0x0); ! target_write_memory(target, 0x200a8000, 4, 128, page_buffer); ! target_write_memory(target, 0x200a8000, 1, 6, oob_buffer); /* write MLC_ECC_AUTO_ENC_REG to start auto encode */ target_write_u32(target, 0x200b8010, 0x0); *************** *** 760,766 **** { struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv; struct target *target = lpc3180_info->target; - uint8_t status = 0x0; if (target->state != TARGET_HALTED) { --- 760,765 ---- *************** *** 768,787 **** return ERROR_NAND_OPERATION_FAILED; } do { if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) { /* Read MLC_ISR, wait for controller to become ready */ target_read_u8(target, 0x200b8048, &status); ! if (status & 2) ! return 1; } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) { /* we pretend that the SLC controller is always ready */ ! return 1; } alive_sleep(1); --- 767,800 ---- return ERROR_NAND_OPERATION_FAILED; } + LOG_DEBUG("lpc3180_controller_ready timeout start=%d",timeout); + do { if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) { + uint8_t status = 0x0; /* Read MLC_ISR, wait for controller to become ready */ target_read_u8(target, 0x200b8048, &status); ! if (status & 2){ ! LOG_DEBUG("lpc3180_controller_ready timeout end=%d",timeout); ! return 1; ! } } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) { + uint32_t status = 0x0; + /* Read SLC_STAT and check READY bit */ + target_read_u32(target, 0x20020018, &status); + + if (status & 1){ + LOG_DEBUG("lpc3180_controller_ready timeout end=%d",timeout); + return 1; + } + /* we pretend that the SLC controller is always ready */ ! // return 1; } alive_sleep(1); *************** *** 801,806 **** --- 814,821 ---- return ERROR_NAND_OPERATION_FAILED; } + LOG_DEBUG("lpc3180_nand_ready timeout start=%d",timeout); + do { if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) *************** *** 810,817 **** /* Read MLC_ISR, wait for NAND flash device to become ready */ target_read_u8(target, 0x200b8048, &status); ! if (status & 1) ! return 1; } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) { --- 825,834 ---- /* Read MLC_ISR, wait for NAND flash device to become ready */ target_read_u8(target, 0x200b8048, &status); ! if (status & 1){ ! LOG_DEBUG("lpc3180_nand_ready timeout end=%d",timeout); ! return 1; ! } } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) { *************** *** 820,827 **** /* Read SLC_STAT and check READY bit */ target_read_u32(target, 0x20020018, &status); ! if (status & 1) ! return 1; } alive_sleep(1); --- 837,846 ---- /* Read SLC_STAT and check READY bit */ target_read_u32(target, 0x20020018, &status); ! if (status & 1){ ! LOG_DEBUG("lpc3180_nand_ready timeout end=%d",timeout); ! return 1; ! } } alive_sleep(1); *************** *** 844,850 **** } unsigned num; ! COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], num); struct nand_device *nand = get_nand_device_by_num(num); if (!nand) { --- 863,869 ---- } unsigned num; ! COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num); struct nand_device *nand = get_nand_device_by_num(num); if (!nand) { diff -crN openocdp1/openocd/tcl/board/hitex_lpc3250.cfg openocdp2/openocd/tcl/board/hitex_lpc3250.cfg *** openocdp1/openocd/tcl/board/hitex_lpc3250.cfg 1970-01-01 01:00:00.000000000 +0100 --- openocdp2/openocd/tcl/board/hitex_lpc3250.cfg 2010-01-10 16:23:27.000000000 +0100 *************** *** 0 **** --- 1,30 ---- + # Hitex eval board for LPC3250 + # http://www.hitex.com/ + + # The board is initialized after reset by boot loader already flashed by the factory. + + source [find target/lpc3250.cfg] + + nand device flash.mem lpc3180 $_TARGETNAME 13000 + + $_TARGETNAME configure -event reset-start { + echo "reset-start...." + # At reset, CPU runs at 32.768 kHz. JTAG frequency must be 6 times slower if + # RCLK is not supported. + # jtag_khz 5 + + #probe the nand flash + halt + lpc3180 select 0 mlc + arm7_9 fast_memory_access enable + nand probe 0 + nand list + + + # RSTC_MR : enable user reset, reset length is 64 slow clock cycles. MMU may + # be enabled... use physical address. + mdw phys 0x40004044 + echo "...end" + } + + diff -crN openocdp1/openocd/tcl/interface/hitex-lpc3250-stick.cfg openocdp2/openocd/tcl/interface/hitex-lpc3250-stick.cfg *** openocdp1/openocd/tcl/interface/hitex-lpc3250-stick.cfg 1970-01-01 01:00:00.000000000 +0100 --- openocdp2/openocd/tcl/interface/hitex-lpc3250-stick.cfg 2010-01-10 16:22:30.000000000 +0100 *************** *** 0 **** --- 1,13 ---- + # + # Hitex LPC325-Stick + # + # http://www.hitex.com/index.php?id=lpc3250-stick-details&L= + # + + + interface ft2232 + + ft2232_device_desc "LPC3250-Stick" + ft2232_layout stm32stick + ft2232_vid_pid 0x0640 0x0026 + diff -crN openocdp1/openocd/tcl/target/lpc3250.cfg openocdp2/openocd/tcl/target/lpc3250.cfg *** openocdp1/openocd/tcl/target/lpc3250.cfg 1970-01-01 01:00:00.000000000 +0100 --- openocdp2/openocd/tcl/target/lpc3250.cfg 2010-01-10 16:22:58.000000000 +0100 *************** *** 0 **** --- 1,55 ---- + + source [find interface/hitex-lpc3250-stick.cfg] + + + + ###################################### + # Target: LPC3250 + ###################################### + + if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME + } else { + set _CHIPNAME lpc3250 + } + + if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN + } else { + set _ENDIAN little + } + + if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID + } else { + # force an error till we get a good number + set _CPUTAPID 0x17900f0f + } + + if { [info exists ETMTAPID ] } { + set _ETMTAPID $ETMTAPID + } else { + # force an error till we get a good number + set _ETMTAPID 0x1b900f0f + } + + jtag_nsrst_delay 100 + jtag_ntrst_delay 200 + + jtag_khz 1000 + + reset_config trst_and_srst + + # + jtag newtap $_CHIPNAME etm -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_ETMTAPID + + jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + + + ###################### + # Target configuration + ###################### + + set _TARGETNAME $_CHIPNAME.cpu + target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs +