On Tue, Jan 26, 2010 at 5:38 AM, David Brownell <[email protected]> wrote: > On Tuesday 19 January 2010, Øyvind Harboe wrote: >> Run the following and it will fail to halt occasionally. This is not a >> regression, >> but I thought I'd post this tip on how to reproduce flaky reset problems... > > Got any more info on this? Just curious.
Here it is: > reset init 10 kHz JTAG tap: str710.cpu tap/device found: 0x3f0f0f0f (mfg: 0x787, part: 0xf0f0, ver: 0x3) srst pulls trst - can not reset into halted mode. Issuing halt after reset. Halt timed out, wake up GDB. timed out while waiting for target halted TARGET: str710.cpu - Not halted Command handler execution failed in procedure 'reset' called at file "command.c", line 647 called at file "command.c", line 361 I need to abuse it a bit to get the debug_level 3 log. Edgar -- Edgar Grimberg System Developer Zylin AS ZY1000 JTAG Debugger http://www.zylin.com/zy1000.html Phone: (+47) 51 63 25 00 _______________________________________________ Openocd-development mailing list [email protected] https://lists.berlios.de/mailman/listinfo/openocd-development
