> About the data cache flush, I'm pretty sure this instruction is not in the > data > cache. What happens when we flush an address that is not in the data cache?
I don't know. Here are some experiments you could run: 1. Use telnet only(no gdb) 2. reset init 3. Modify some ram address to have a few instructions 4. modify PC to that address 5. step one instruction. Use the arm920 commands to verify the contents of the cache 6. use the mrc/mcr/mww/virt2phys commands to modify the instructions the CPU is about to execute & flush cache, etc. read arm920 on cache coherency. 7. once you have the telnet commands to implement proper breakpoint handling, post it and we can easily translate it to C... :-) -- Øyvind Harboe Visit us at Embedded World, March 2nd-4th. IS2T's stand, HALL 10 - 118 http://www.zylin.com/events_embeddedworld.html US toll free 1-866-980-3434 / International +47 51 63 25 00 http://www.zylin.com/zy1000.html ARM7 ARM9 ARM11 XScale Cortex JTAG debugger and flash programmer _______________________________________________ Openocd-development mailing list [email protected] https://lists.berlios.de/mailman/listinfo/openocd-development
