I don't have a phytec board to test on handy(if someone wants to send us one it would be greatly appreciated!).
Attached is a patch that tries to cleanup target/board scripts a bit, but I really rely on the list to test, polish comments & feed back a suitable version to be merged. -- Øyvind Harboe Visit us at Embedded World, March 2nd-4th. IS2T's stand, HALL 10 - 118 http://www.zylin.com/events_embeddedworld.html US toll free 1-866-980-3434 / International +47 51 63 25 00 http://www.zylin.com/zy1000.html ARM7 ARM9 ARM11 XScale Cortex JTAG debugger and flash programmer
From 260e2f2eddc2f67019d1e5196ee4c850404043b7 Mon Sep 17 00:00:00 2001 From: =?utf-8?q?=C3=98yvind=20Harboe?= <oyv...@minizy1000.(none)> Date: Sun, 28 Feb 2010 19:53:08 +0100 Subject: [PATCH] lpc3250: cleanups of target/board script MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Make the scripts more generic. Whether or not to reset upon GDB connect is a user decision, not something that belongs in the board config. Signed-off-by: Øyvind Harboe <[email protected]> --- tcl/board/phytec_lpc3250.cfg | 2 - tcl/target/lpc3250.cfg | 55 +++++++++++++++++++++++++++++------------- 2 files changed, 38 insertions(+), 19 deletions(-) diff --git a/tcl/board/phytec_lpc3250.cfg b/tcl/board/phytec_lpc3250.cfg index 78cb90d..5d3fbf9 100644 --- a/tcl/board/phytec_lpc3250.cfg +++ b/tcl/board/phytec_lpc3250.cfg @@ -7,8 +7,6 @@ reset_config trst_and_srst separate arm7_9 dcc_downloads enable -$_TARGETNAME configure -event gdb-attach { reset init } - $_TARGETNAME configure -event reset-start { arm7_9 fast_memory_access disable jtag_khz 200 diff --git a/tcl/target/lpc3250.cfg b/tcl/target/lpc3250.cfg index e902fb4..09c984e 100644 --- a/tcl/target/lpc3250.cfg +++ b/tcl/target/lpc3250.cfg @@ -1,36 +1,57 @@ -# lpc3250 config -# +# NXP LPC3250 -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME lpc3250 +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME LPC3250 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { set _ENDIAN little } if { [info exists CPUTAPID ] } { set _CPUTAPID $CPUTAPID } else { - set _CPUTAPID 0x17900f0f + # force an error till we get a good number + set _CPUTAPID 0x17900F0F } -if { [info exists SJCTAPID ] } { - set _SJCTAPID $SJCTAPID +if { [info exists ETBTAPID ] } { + set _ETBTAPID $ETBTAPID } else { - set _SJCTAPID 0x1b900f0f + # force an error till we get a good number + set _ETBTAPID 0x1B900F0F } -jtag newtap $_CHIPNAME sjc -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_SJCTAPID +# 10ms for the osc to stable + +jtag_khz 200 + +reset_config trst_and_srst +jtag_nsrst_delay 200 +jtag_ntrst_delay 200 +jtag_ntrst_assert_width 100 +jtag_nsrst_assert_width 100 + +# TAP Target +jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_ETBTAPID jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +# CPU Target set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm926ejs -endian little -chain-position $_TARGETNAME -work-area-phys 0x00000000 -work-area-size 0x7d0000 -work-area-backup 0 +target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs +$_TARGETNAME configure -work-area-phys 0x00030000 -work-area-size 0x10000 -work-area-backup 1 + +$_TARGETNAME configure -event reset-init { + mww 0x40004014 1 +} -proc power_restore {} { puts "Sensed power restore. No action." } -proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." } +$_TARGETNAME configure -event reset-start { + # At reset, CPU runs at 13MHz. + # JTAG frequency must be 6 times slower if RCLK is not supported. + jtag_khz 2000 +} -- 1.6.3.3
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