From: Mike Dunn <[email protected]>
Fix problem with the xscale icache and dcache commands. Both commands were
enabling or disabling the mmu, not the caches
---
Hi David, et.al. I didn't look any further after my earlier patch fixed the
trivial problem with command argument parsing. Turns out the underlying code
was broken. The resolution is straightforward when you look at the arguments to
xscale_enable_mmu_caches() and xscale_disable_mmu_caches(). I finally took a
deeper look after dumping the cp15 control register (XSCALE_CTRL) and seeing
that the cache bits weren't changing, but the mmu bit was (which caused all
manner of grief, as you can imagine). This has been tested and works OK now.
src/target/xscale.c | 17 +++++++++++------
1 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 50c9595..08797f1 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -3204,14 +3204,19 @@ COMMAND_HANDLER(xscale_handle_idcache_command)
{
bool enable;
COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable);
- if (enable)
- xscale_enable_mmu_caches(target, 1, 0, 0);
- else
- xscale_disable_mmu_caches(target, 1, 0, 0);
- if (icache)
+ if (icache) {
xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled =
enable;
- else
+ if (enable)
+ xscale_enable_mmu_caches(target, 0, 0, 1);
+ else
+ xscale_disable_mmu_caches(target, 0, 0, 1);
+ } else {
xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled =
enable;
+ if (enable)
+ xscale_enable_mmu_caches(target, 0, 1, 0);
+ else
+ xscale_disable_mmu_caches(target, 0, 1, 0);
+ }
}
bool enabled = icache ?
--
1.6.4.4
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