Hello,

I'm currently an intern in the engineering school of Fribourg ( EIA ).
I'm working on an armadeus development board APF27Dev 1.2 with an IMX27
processor on board ( ARM9 core ).
I would like to use the jtag interface with openocd (0.4.0
(2010-06-15-14:46) ) and two usb-jtag probes ( Amontec JTAGKEY2, Olimex
ARM-USB-OCD ).
The configuration scripts used for my job are attached with this mail :
-45-libftdi.rules contains script for udev to set the correct IDs for
the probe.
-apf27.cfg and imx27.cfg are configuration scripts for the board and the
processor
-imxapf27 is the script used in the opendocd command line, regrouping
the two previous configuration scripts.
-jtagkey2.cfg is configuration file of the corresponding probe provided
by default but added with a speed limit line at the end ( 15000kHz ) for
better working success.
-testLed.ocd is a test file to show that jtag is working correcting by
controlling step by step the program, the LED D14 should light on if the
jtag communication is successing.

This is the used command line for openocd :
openocd -f /usr/local/share/openocd/scripts/imxapf27.cfg -f testLed.ocd

The problem is :
Me and my partner are testing these two probes on the same board
similarly configured. For my part, even if I test the Olimex and
Jtagkey2, I got the same bad result. My partner, for her part have the
good following expected result with jtagkey2 :

        openocd -f /usr/local/share/openocd/scripts/imxapf27.cfg -f
        testLed.ocd
        Open On-Chip Debugger 0.4.0 (2010-06-15-14:46)
        Licensed under GNU GPL v2
        For bug reports, read
                http://openocd.berlios.de/doc/doxygen/bugs.html
        force soft breakpoints
        trst_and_srst srst_pulls_trst srst_gates_jtag trst_push_pull
        srst_open_drain
        dcc downloads are enabled
        fast memory access is enabled
        15000 kHz
           TapName             Enabled  IdCode     Expected   IrLen
        IrCap IrMask
        -- ------------------- -------- ---------- ---------- -----
        ----- ------
         0 imx27.etb              Y     0x00000000 0x1b900f0f     4 0x01
        0x0f
         1 imx27.cpu              Y     0x00000000 0x07926121     4 0x01
        0x0f
         2 xc3s200a.fpga.fpga     Y     0x00000000 0x02218093     6 0x35
        0x3f
        Info : max TCK change to: 30000 kHz
        Info : clock speed 15000 kHz
        Info : JTAG tap: imx27.etb tap/device found: 0x1b900f0f (mfg:
        0x787, part: 0xb900, ver: 0x1)
        Info : JTAG tap: imx27.cpu tap/device found: 0x07926121 (mfg:
        0x090, part: 0x7926, ver: 0x0)
        Info : JTAG tap: xc3s200a.fpga.fpga tap/device found: 0x02218093
        (mfg: 0x049, part: 0x2218, ver: 0x0)
        Info : Embedded ICE version 6
        Info : imx27.cpu: hardware has 2 breakpoint/watchpoint units
        Info : ETM v1.3


Now, this is my problem with the jtagkey2 connected with my board :

        openocd -f /usr/local/share/openocd/scripts/imxapf27.cfg -f -d 3
        testLed.ocd
        
        Open On-Chip Debugger 0.4.0 (2010-06-15-14:46)
        Licensed under GNU GPL v2
        For bug reports, read
                http://openocd.berlios.de/doc/doxygen/bugs.html
        force soft breakpoints
        trst_and_srst srst_pulls_trst srst_gates_jtag trst_push_pull
        srst_open_drain
        dcc downloads are enabled
        fast memory access is enabled
        15000 kHz
           TapName             Enabled  IdCode     Expected   IrLen
        IrCap IrMask
        -- ------------------- -------- ---------- ---------- -----
        ----- ------
         0 imx27.etb              Y     0x00000000 0x1b900f0f     4 0x01
        0x0f
         1 imx27.cpu              Y     0x00000000 0x07926121     4 0x01
        0x0f
         2 xc3s200a.fpga.fpga     Y     0x00000000 0x02218093     6 0x35
        0x3f
        Info : max TCK change to: 30000 kHz
        Info : clock speed 15000 kHz
        Info : JTAG tap: imx27.etb tap/device found: 0x1b900f0f (mfg:
        0x787, part: 0xb900, ver: 0x1)
        Info : JTAG tap: imx27.cpu tap/device found: 0x07926121 (mfg:
        0x090, part: 0x7926, ver: 0x0)
        Info : JTAG tap: xc3s200a.fpga.fpga tap/device found: 0x02218093
        (mfg: 0x049, part: 0x2218, ver: 0x0)
        Info : Embedded ICE version 15
        Error: unknown EmbeddedICE version (comms ctrl: 0xfffffffc)
        Info : imx27.cpu: hardware has 2 breakpoint/watchpoint units
        Warn : ETMv2+ support is incomplete
        Info : ETM v16.15
        Segmentation fault

As you can see, the Embedded ICE version used in my case is not the same
as the one used by my partner (15 instead of 6), although we have the
same version of openocd, same configuration files, and the same board !
I don't know how is selected the embedded ICE version and how openocd
use that. I also don't know why i get a segmentation fault error at the
end...

Could you help me ? I wish I provided you all information and files you
need.

Nicolas Daviot

BUS!="usb", ACTION!="add", SUBSYSTEM!=="usb_device", GOTO="kcontrol_rules_end" 

SYSFS{idProduct}=="cff8", SYSFS{idVendor}=="0403", MODE="664", GROUP="plugdev" 
 
LABEL="kcontrol_rules_end" 
#GNB and configuration
gdb_port 3333
gdb_breakpoint_override soft
telnet_port 4444

# Hardware configuration, uses given scripts
source [find cpu/arm/imx27.cfg]
source [find board/apf27.cfg]
source [find interface/jtagkey2.cfg]
#source [find interface/olimex-arm-usb-ocd.cfg]

scan_chain

# Starts the chain initialization
init
# Board # 
#########
jtag newtap xc3s200a.fpga fpga \
        -irlen 6 \
        -irmask 0x3f \
        -ircapture 0x35 \
        -expected-id 0x02218093

$_TARGETNAME configure -event reset-init { apf27_init }

proc apf27_init { } {
        # This setup puts RAM at 0xA0000000
 
        # reset the board correctly
        #reset run
        #reset halt
 
  # reset keeping fpga alive
        soft_reset_halt 
        halt
 
 
        mww 0x10000000 0x20040304
        mww 0x10020000 0x00000000
        mww 0x10000004 0xDFFBFCFB
        mww 0x10020004 0xFFFFFFFF
 
        sleep 100
 
        # ========================================
        #  Configure DDR on CSD0 -- initial reset
        # ========================================
        mww 0x10027818 0x0000080F 
        mww 0xD8001010 0x0000000C 
 
        # ========================================
        #  Configure DDR on CSD0 -- wait 5000 cycle 
        # ========================================
        mww 0x10027828 0x55555555 
        mww 0x10027830 0x55555555 
        mww 0x10027834 0x55555555 
        mww 0x10027838 0x00005005 
        mww 0x1002783C 0x15555555 
 
        mww 0xD8001004 0x00695728
 
        mww 0xD8001000 0x92100000 
        mww 0xA0000F00 0x0
 
        mww 0xD8001000 0xA2100000 
        mww 0xA0000F00 0x0
        mww 0xA0000F00 0x0
        mww 0xA0000F00 0x0
        mww 0xA0000F00 0x0
 
        mww 0xD8001000 0xA2100000 
        mww 0xA0000F00 0x0
        mww 0xA0000F00 0x0
        mww 0xA0000F00 0x0
        mww 0xA0000F00 0x0
 
        mww 0xD8001000 0xB2100000 
        mwb 0xA0000033 0xDA
        mwb 0xA2000000 0x00
 
        mww 0xD8001000 0x82126080 
}

# page 3-34 of "MCIMC27 Multimedia Applications Processor Reference Manual, Rev 
0.3" 
# SRST pulls TRST 
# 
# Without setting these options correctly you'll see all sorts 
# of weird errors, e.g. MOE=0xe, invalid cpsr values, reset 
# failing, etc. 
reset_config trst_and_srst srst_pulls_trst 

if { [info exists CHIPNAME] } { 
   set  _CHIPNAME $CHIPNAME 
} else { 
   set  _CHIPNAME imx27 
} 



if { [info exists ENDIAN] } { 
   set  _ENDIAN $ENDIAN 
} else { 
   set  _ENDIAN little 
} 


# Note above there are 2 taps 

# trace buffer  
if { [info exists ETBTAPID ] } { 
   set _ETBTAPID $ETBTAPID 
} else { 
   set _ETBTAPID 0x1b900f0f 
} 

jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETBTAPID 

# The CPU tap 
if { [info exists CPUTAPID ] } { 
   set _CPUTAPID $CPUTAPID 
} else { 
   set _CPUTAPID 0x07926121 
} 
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 
$_CPUTAPID 

# Create the GDB Target. 
set _TARGETNAME $_CHIPNAME.cpu 
target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position 
$_TARGETNAME -variant arm926ejs
# REVISIT what operating environment sets up this virtual address mapping? 
$_TARGETNAME configure -work-area-virt 0xffff4c00 -work-area-phys 0xffff4c00 
-work-area-size 0x8000 -work-area-backup 1 
# Internal to the chip, there is 45K of SRAM 
# 

arm7_9 dcc_downloads enable 
arm7_9 fast_memory_access enable 

# trace setup 
etm config $_TARGETNAME 16 normal full etb 
etb config $_TARGETNAME $_CHIPNAME.etb


proc initLed {} {
  mwh 0x10015540 0x0000
  mwh 0x10015500 0x4000
  mwh 0x10015538 0x0000
  mwh 0x10015520 0x4000
  mww 0x10015504 0x30000000
}

proc ledOn {} {
  mwh 0x1001551c 0x0000
}

proc ledOff {} {
  mwh 0x1001551c 0x4000
}
#
# Amontec JTAGkey2
#
# http://www.amontec.com/jtagkey2.shtml
#

interface ft2232
ft2232_device_desc "Amontec JTAGkey-2"
ft2232_layout jtagkey
ft2232_vid_pid 0x0403 0xCFF8
jtag_khz 15000

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