Comments? -- Øyvind Harboe US toll free 1-866-980-3434 / International +47 51 63 25 00 http://www.zylin.com/zy1000.html ARM7 ARM9 ARM11 XScale Cortex JTAG debugger and flash programmer
From 3a3ab896c350ff5a177837561b3042c12e3fc7c3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= <[email protected]> Date: Sat, 7 Aug 2010 22:07:56 +0200 Subject: [PATCH] lpc1768: slower safer default settings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit
srst does not pull trst on the lpc1768 I tried(Keil PCB), reset halt works fine. reduce default frequency to 100kHz and leave comment that a decent PCB specific script should increase the chip frequency in reset-init Signed-off-by: Øyvind Harboe <[email protected]> --- tcl/target/lpc1768.cfg | 13 ++++++++----- 1 files changed, 8 insertions(+), 5 deletions(-) diff --git a/tcl/target/lpc1768.cfg b/tcl/target/lpc1768.cfg index ff92e4a..cd67b14 100644 --- a/tcl/target/lpc1768.cfg +++ b/tcl/target/lpc1768.cfg @@ -28,8 +28,7 @@ if { [info exists CPUTAPID ] } { adapter_nsrst_delay 200 jtag_ntrst_delay 200 -# LPC2000 & LPC1700 -> SRST causes TRST -reset_config srst_pulls_trst +reset_config trst_and_srst srst_nogate jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID @@ -54,9 +53,13 @@ flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME \ # Although rclk "appears to work", it turns out that this yields # 4MHz whereas the "correct" rate is CCLK/6, which is not what # you get with rclk. -jtag_khz [ expr 4000 / 6 ] - - +# +# Experimentation shows that we have to use as low as 100kHz for +# 4MHz parts to ensure that reset works properly. A decent +# PCB specific configuration file should increase the JTAG clock +# rate during reset-init after having switched from RC oscilator +# to a faster clock. +jtag_khz 100 $_TARGETNAME configure -event reset-init { # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select -- 1.7.0.4
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