From: Thomas Koeller <[email protected]> The PLL pre- and postdividers seem to have enable bits, although these are not mentioned in the chip documentation.
Signed-off-by: Thomas Koeller <[email protected]> --- tcl/target/davinci.cfg | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/tcl/target/davinci.cfg b/tcl/target/davinci.cfg index 31750dd..2267809 100644 --- a/tcl/target/davinci.cfg +++ b/tcl/target/davinci.cfg @@ -179,7 +179,7 @@ proc pll_v03_setup {pll_addr mult config} { mww [expr $pll_addr + 0x0110] [expr ($mult / 2) & 0x1ff] if { [dict exists $config prediv] } { set div [dict get $config prediv] - set div [expr ($div - 1)] + set div [expr 0x8000 | ($div - 1)] mww [expr $pll_addr + 0x0114] $div } if { [dict exists $config postdiv] } { -- 1.7.1 _______________________________________________ Openocd-development mailing list [email protected] https://lists.berlios.de/mailman/listinfo/openocd-development
