Below is the story as I understand it: The JTAG is connected to a bus master that can write directly to physical memory for the Cortex series.
This means that there are at least three ways to write to memory: 1. physical write. I believe this is implemented as talking directly to the JTAG circuitry that is a bus master and the CPU is not involved when writing to memory. A lot of debug circuitry is memory mapped and therefore writing to physical memory bypassing the CPU is necessary to e.g. reset the CPU. 2. writing to a virtual address. Here the CPU *must* be halted and the CPU does the writing. Writes can fail if e.g. the MMU has marked ram as read only. 3. have the CPU write to physical memory. When the MMU is disabled and the CPU is halted, this should be identical to #1, but I don't know why #3 would be used in favor of #1. Could #1 and #3 have important differences on a multcore system??? -- Øyvind Harboe US toll free 1-866-980-3434 / International +47 51 63 25 00 http://www.zylin.com/zy1000.html ARM7 ARM9 ARM11 XScale Cortex JTAG debugger and flash programmer _______________________________________________ Openocd-development mailing list [email protected] https://lists.berlios.de/mailman/listinfo/openocd-development
