Hi Jorg, That's what I don't understand .. You get reliable debugging with 500Khz, but with me I have to set the PLL running and then set the cpu clock to 100mhz before I can get high speed debugging ... With the rc osc (I presume at 4mhz) on boot, I CANNOT get reliable operation unless I drop my JTAG speed down to <=20Khz ..
What JTAG adapter are you using, is it FT2232 based?, if so, can you tell me if it is similar to the Turtilizer2 open-hardware adapter that I am using? I would like to understand the differences between your setup and mine .. Cheers, Bernie ------------------------------------------------------------------------------------------ Hiding the Truth with "Political Correctness" is the same as Lying ... BRM -----Original Message----- From: [email protected] [mailto:[email protected]] On Behalf Of Jörg Fischer Sent: Friday, 15 October 2010 8:32 a.m. To: [email protected] Subject: Re: [Openocd-development] Problem getting reliable "reset init" on LPC1766 target. Hi, Am 13.10.2010 08:23, schrieb Øyvind Harboe: > 2010/10/13 Jörg Fischer <[email protected]>: >> This work for me _reliable_ on a custom lpc1768 board: >> >> adapter_khz 500 >> >> #delays on reset lines >> adapter_nsrst_delay 30 >> adapter_nsrst_assert_width 100 >> >> jtag_ntrst_delay 2 >> jtag_ntrst_assert_width 100 >> >> reset_config srst_only separate >> >>[...] > Interesting! > > Did you try an operation 100 times? Once or twice doesn't make it robust! > > Paste this into Telnet: > > for {set i 0} {$i < 100} {set i [expr $i+1]} {echo "Reseting $i"; > reset init} [x] Done. I had no error message whatsoever. So it should be safe to say: "It works reliable". -- J. Fischer _______________________________________________ Openocd-development mailing list [email protected] https://lists.berlios.de/mailman/listinfo/openocd-development _______________________________________________ Openocd-development mailing list [email protected] https://lists.berlios.de/mailman/listinfo/openocd-development
