billium wrote:
> I had a problem with lm3s6965:
>
> Open On-Chip Debugger 0.5.0-dev-00565-g4617cd0 (2010-10-28-19:55)
> Info : JTAG tap: lm3s6965.cpu tap/device found: 0x000000ff (mfg: 0x07f, part:
> 0x0000, ver: 0x0)
> Warn : JTAG tap: lm3s6965.cpu UNEXPECTED: 0x000000ff (mfg: 0x07f, part:
> 0x0000, ver: 0x0)
> Error: JTAG tap: lm3s6965.cpu expected 1 of 1: 0x0ba00477 (mfg: 0x23b, part:
> 0xba00, ver: 0x0)
Looks bad. :\
> A laptop with 0.5.0-dev-00445-g1143bbc (2010-07-20-09:22) works o.k., so
> I copied the stellaris.cfg from working laptop to desktop. Openocd back
> in action for Stellaris. :)
Hm. Can you check what changes in the cfg file made it break? The
1143bbc..4617cd0 diff is attached. Please try adding each change in
to your working file and see where it breaks?
Which JTAG interface are you using?
//Peter
diff --git a/tcl/target/stellaris.cfg b/tcl/target/stellaris.cfg
index 5f4428f..e206a9c 100644
--- a/tcl/target/stellaris.cfg
+++ b/tcl/target/stellaris.cfg
@@ -1,5 +1,12 @@
# TI/Luminary Stellaris LM3S chip family
+# Luminary chips support both JTAG and SWD transports.
+# Adapt based on what transport is active.
+source [find target/swj-dp.tcl]
+
+# For now we ignore the SPI and UART options, which
+# are usable only for ISP style initial flash programming.
+
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
@@ -18,22 +25,31 @@ if { [info exists CPUTAPID ] } {
set _CPUTAPID 0x0ba00477
}
+# SWD DAP, and JTAG TAP, take same params for now;
+# ... even though SWD ignores all except TAPID, and
+# JTAG shouldn't need anything more then irlen. (and TAPID).
+swj_newdap $_CHIPNAME cpu -irlen 4 -irmask 0xf \
+ -expected-id $_CPUTAPID -ignore-version
+
+if { [info exists WORKAREASIZE ] } {
+ set _WORKAREASIZE $WORKAREASIZE
+} else {
+ # default to 8K working area
+ set _WORKAREASIZE 0x2000
+}
+
jtag newtap $_CHIPNAME cpu -irlen 4 -irmask 0xf \
-expected-id $_CPUTAPID -ignore-version
-# The "lm3s" variant uses a software reset rather than SRST.
-# This stops the debug registers from being cleared; it works
-# around an erratum which should be fixed in later silicon.
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu \
- -variant lm3s
+target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu
# 8K working area at base of ram, not backed up
#
# NOTE: you may need or want to reconfigure the work area;
# some parts have just 6K, and you may want to use other
# addresses (at end of mem not beginning) or back it up.
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x2000
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size
$_WORKAREASIZE
# JTAG speed ... slow enough to work with a 12 MHz RC oscillator;
# LM3S parts don't support RTCK
@@ -42,7 +58,36 @@ $_TARGETNAME configure -work-area-phys 0x20000000
-work-area-size 0x2000
# configures and enables the PLL. Or you might need to decrease
# this, if you're using a slower clock.
adapter_khz 500
-$_TARGETNAME configure -event reset-start {adapter_khz 500}
+
+source [find mem_helper.tcl]
+
+$_TARGETNAME configure -event reset-start {
+ adapter_khz 500
+
+ #
+ # When nRST is asserted on most Stellaris devices, it clears some of
+ # the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong;
+ # and OpenOCD depends on those TRMs. So we won't use SRST on those
+ # chips. (Only power-on reset should affect debug state, beyond a
+ # few specified bits; not the chip's nRST input, wired to SRST.)
+ #
+ # REVISIT current errata specs don't seem to cover this issue.
+ # Do we have more details than this email?
+ # https://lists.berlios.de/pipermail
+ # /openocd-development/2008-August/003065.html
+ #
+
+ set device_class [expr (([mrw 0x400fe000] >> 16) & 0xff)]
+ if {$device_class == 0 || $device_class == 1 || $device_class == 3} {
+ # Sandstorm, Fury and DustDevil are able to use NVIC SYSRESETREQ
+ cortex_m3 reset_config sysresetreq
+ } else {
+ # Tempest and newer default to using NVIC VECTRESET
+ # this does mean a reset-init event handler is required to reset
+ # any peripherals
+ cortex_m3 reset_config vectreset
+ }
+}
# flash configuration ... autodetects sizes, autoprobed
flash bank $_CHIPNAME.flash stellaris 0 0 0 0 $_TARGETNAME
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