Paul Richards <[email protected]> writes:
> Are there any plans to add support for the Marvell Armada processor
> family to Open OCD? (A hybrid of Feroceon and XScale processors from
> what I understand).
>
> I've had a little success customising scripts to communicate with an
> Armada PXA168 target via a FT4232 interface, though I believe code
> additions will be required. Although new to OpenOCD I'm willing to
> contribute what I can if no similar activities are already underway.
Base operations are already possible by
---
jtag newtap $_CHIPNAME aux -irlen 1 -ircapture 0x1 -irmask 0x01 -disable
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -disable
jtag newtap $_CHIPNAME bs -irlen 9 -ircapture 0x1 -irmask 0x1ff -expected-id
$_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
jtag configure $_CHIPNAME.aux -event tap-enable {}
jtag configure $_CHIPNAME.cpu -event tap-disable "
irscan $_CHIPNAME.bs 0x98
drscan $_CHIPNAME.bs 16 0x00
jtag tapdisable $_CHIPNAME.aux
"
jtag configure $_CHIPNAME.cpu -event tap-enable "
jtag tapenable $_CHIPNAME.aux
irscan $_CHIPNAME.bs 0x98
drscan $_CHIPNAME.bs 16 0x0a
"
jtag configure $_CHIPNAME.bs -event setup "
jtag tapenable $_CHIPNAME.cpu
"
target create $_TARGETNAME dragonite -endian $_ENDIAN -chain-position
$_TARGETNAME
---
see [1] for full configuration. The trick is the first dummy TAP which
is mentioned in some errata entry (an extra TDO is shifted in concatening
mode).
I wrote a NAND driver for the PXA168 (see [2]; PXA320 should be very
similar btw) but it is very slow and although I intended to keep it as
general as possible, I ended with hardcoding certain values of the used
NAND chip. Bad block management is missing too.
Enrico
Footnotes:
[1] http://www.cvg.de/people/ensc/trizeps6.conf
[2] https://github.com/ensc/openocd/commits/master
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