Sorry Laurent, I'm again here with other problems.
as I wrote you, openocd now recognizes the correct TAP but once I open
the telnet session and try to issue simple commands like a soft reset,
I get communication errors.
When I start openocd, I get the following output:
-----------
$ openocd
Open On-Chip Debugger 0.4.0 (2010-12-02-11:35)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.berlios.de/doc/doxygen/bugs.html
trst_and_srst separate srst_gates_jtag trst_push_pull srst_open_drain
jtag_nsrst_delay: 100
jtag_ntrst_delay: 100
100 kHz
Command handler execution failed
Info : device: 6 "2232H"
Info : deviceID: 67358712
Info : SerialNumber: 53SDIXUSA
Info : Description: Amontec JTAGkey-2 A
Info : max TCK change to: 30000 kHz
Info : clock speed 100 kHz
Info : JTAG tap: netx500.cpu tap/device found: 0x07926021 (mfg: 0x010,
part: 0x7926, ver: 0x0)
Info : Embedded ICE version 6
Info : netx500.cpu: hardware has 2 breakpoint/watchpoint units
Info : accepting 'telnet' connection from 0
---------------
please note clock speed, I tried to lower it down to 100 khz to see if
it was simply matter of jtag speed. The messages looks good so I
opened a telnet session and tried to issue a "targets" command, the
following is the output:
-------------
TargetName Type Endian TapName State
-- ------------------ ---------- ------ ------------------ ------------
0* netx500.cpu arm926ejs little netx500.cpu running
--------------
The following is the result of a "reg" command. No values appear:
--------------
===== ARM registers
(0) r0 (/32)
(1) r1 (/32)
(2) r2 (/32)
(3) r3 (/32)
(4) r4 (/32)
(5) r5 (/32)
(6) r6 (/32)
(7) r7 (/32)
(8) r8 (/32)
(9) r9 (/32)
(10) r10 (/32)
(11) r11 (/32)
(12) r12 (/32)
(13) sp_usr (/32)
(14) lr_usr (/32)
(15) pc (/32)
(16) r8_fiq (/32)
(17) r9_fiq (/32)
(18) r10_fiq (/32)
(19) r11_fiq (/32)
(20) r12_fiq (/32)
(21) sp_fiq (/32)
(22) lr_fiq (/32)
(23) sp_irq (/32)
(24) lr_irq (/32)
(25) sp_svc (/32)
(26) lr_svc (/32)
(27) sp_abt (/32)
(28) lr_abt (/32)
(29) sp_und (/32)
(30) lr_und (/32)
(31) cpsr (/32)
(32) spsr_fiq (/32)
(33) spsr_irq (/32)
(34) spsr_svc (/32)
(35) spsr_abt (/32)
(36) spsr_und (/32)
===== EmbeddedICE registers
(37) debug_ctrl (/6): 0x00
(38) debug_status (/10)
(39) comms_ctrl (/6)
(40) comms_data (/32)
(41) watch_0_addr_value (/32)
(42) watch_0_addr_mask (/32)
(43) watch_0_data_value (/32)
(44) watch_0_data_mask (/32)
(45) watch_0_control_value (/9)
(46) watch_0_control_mask (/8)
(47) watch_1_addr_value (/32)
(48) watch_1_addr_mask (/32)
(49) watch_1_data_value (/32)
(50) watch_1_data_mask (/32)
(51) watch_1_control_value (/9)
(52) watch_1_control_mask (/8)
(53) vector_catch (/8)
------------------------
then a "reset halt":
------------------------
Info : TAP netx500.cpu does not have IDCODE
Warn : JTAG tap: netx500.cpu UNEXPECTED: 0x00000000 (mfg: 0x000,
part: 0x0000, ver: 0x0)
Error: JTAG tap: netx500.cpu expected 1 of 1: 0x07926021 (mfg: 0x010,
part: 0x7926, ver: 0x0)
Warn : Unexpected idcode after end of chain: 1 0x00000008
Warn : Unexpected idcode after end of chain: 33 0x30108104
Warn : Unexpected idcode after end of chain: 65 0x007f83c9
Warn : Unexpected idcode after end of chain: 97 0x007f8000
Warn : Unexpected idcode after end of chain: 129 0x007f8000
Warn : Unexpected idcode after end of chain: 161 0x007f8000
Warn : Unexpected idcode after end of chain: 193 0x007f8000
Warn : Unexpected idcode after end of chain: 225 0x007f8000
Warn : Unexpected idcode after end of chain: 257 0x007f8000
Warn : Unexpected idcode after end of chain: 289 0x007f8000
Warn : Unexpected idcode after end of chain: 321 0x007f8000
Warn : Unexpected idcode after end of chain: 353 0x007f8000
Warn : Unexpected idcode after end of chain: 385 0x007f8000
Warn : Unexpected idcode after end of chain: 417 0x007f8000
Warn : Unexpected idcode after end of chain: 449 0x007f8000
Warn : Unexpected idcode after end of chain: 481 0x007f8000
Warn : Unexpected idcode after end of chain: 513 0x007f8000
Warn : Unexpected idcode after end of chain: 545 0x007f8000
Warn : Unexpected idcode after end of chain: 577 0x007f8000
Error: double-check your JTAG setup (interface, speed, missing TAPs, ...)
error: -100
Command handler execution failed
-------------------
if I execute a power reset, unplug and plug usb again and launch
openocd doing no other operations, after a minute or two will appear
sequences of message like:
--------------------
Error: invalid mode value encountered 0
Error: cpsr contains invalid mode value - communication failure
Error: invalid mode value encountered 0
Error: cpsr contains invalid mode value - communication failure
Error: invalid mode value encountered 0
Error: cpsr contains invalid mode value - communication failure
Error: invalid mode value encountered 0
Error: cpsr contains invalid mode value - communication failure
Error: invalid mode value encountered 0
Error: cpsr contains invalid mode value - communication failure
Error: invalid mode value encountered 0
Error: cpsr contains invalid mode value - communication failure
Error: invalid mode value encountered 0
Error: cpsr contains invalid mode value - communication failure
Error: invalid mode value encountered 0
Error: cpsr contains invalid mode value - communication failure
Error: invalid mode value encountered 0
Error: cpsr contains invalid mode value - communication failure
Error: invalid mode value encountered 0
Error: cpsr contains invalid mode value - communication failure
Error: couldn't read enough bytes from FT2232 device (5 < 6)
Error: couldn't read from FT2232
Error: FT_Write returned: 4
Error: couldn't write MPSSE commands to FT2232
Error: FT_Write returned: 4
Error: couldn't write MPSSE commands to FT2232
Error: FT_Write returned: 4
---------------------
my hope is that, as happened in my last mail, all these messages have
a unique reason that could be fixed with some configuration magic.
Cheers
Massimo
[....]
> Yes, but it is like that.
>
> Anyway, it is not really a fault from you or from any script. It is really
> coming from OpenOCD.
> OpenOCD should start at a lower frequency first (a lot of software start at
> 1MHZ). And then OpenOCD should auto-detect the max JTAG TCK frequency ....
>
> Max JTAG Frequency depends on :
> - JTAG TAP technology
> - JTAG Chain (number of TAPs, lenght of the chain)
> - JTAG buffers quality
> - JTAG signal integrity
> - JTAG adapter itself
>
> Regards,
> Laurent
> http://www.amontec.com
>
>
>
> _______________________________________________
> Openocd-development mailing list
> [email protected]
> https://lists.berlios.de/mailman/listinfo/openocd-development
>
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