HI all, I have a simple question for anyone worked with MIPS (EJTAG) before - does it support "halt" mode debugging, or ROM monitor mode is only option ?
Coming from the ARM world, I am looking for "halt" mode debugging, as I am very limited on chip surface to add additional ROM. 1) I read in one document : In addition to providing a standard debug I/O interface, EJTAG provides the following new capabilities for software and system debug: - Off-board EJTAG memory - A MIPS processor in Debug Mode sees EJTAG memory mapped as physical memory, but references to this memory are converted into transactions on the TAP interface. Both instructions and data can be accessed in EJTAG memory, which allows debugging of systems without requiring the presence of a ROM monitor or debugger scratch pad RAM. Would that mean that all CPU-s internal state can be explored using TAP and without monitor ROM ? 2) In Software Users Manual it is written : The TAP modules support handling of fetches, loads and stores from the CPU through the dmseg segment, whereby the TAP module can operate like a slave unit connected to the on-chip bus. The core can then execute code taken from the EJTAG Probe and it can access data (via a load or store) which is located on the EJTAG Probe. This occurs in a serial way through the EJTAG interface: the core can thus execute instructions e.g. debug monitor code, without occupying the memory. What would that say, I do not quite get... That ROM monitor is finally necessary, and there is no "halt" mode debugging ? 3) Here : http://www.linux-mips.org/wiki/JTAG is written : MIPS EJTAG has two modes, one is "DMA" mode where the JTAG can cause CPU bus cycles directly, the other "PrAcc" is where the JTAG interface is used to respond to CPU memory accesses in a special range of memory (DMSEG, 0xFF200000) and you have to write little bits of MIPS code to do what you want and emulate that memory on the host side. All systems support PrAcc mode by nature. The DMA mode is optional and not as widely supported as the normal mode. The presence of DMA mode is noted in the IMPCODE register. Can anyone explain me what this would say " JTAG can cause CPU bus cycles directly" ? Can anyone confirm me that " 'PrAcc' is where the JTAG interface is used to respond to CPU memory accesses in a special range of memory (DMSEG, 0xFF200000) ", which I do not quite get, would actually say that " ROM monitor is called when breakpoint exception is hit " and explain what "emulate that memory on the host side" would say (I have no idea)... Thank you very much and best regards, Drasko _______________________________________________ Openocd-development mailing list [email protected] https://lists.berlios.de/mailman/listinfo/openocd-development
