Hi Luca,
On 10 February 2011 06:19, Luca Ellero <[email protected]> wrote:
> This patch adds read/write capability to memory addresses not
> accessible through AHB-AP (for example "boot ROM code").
>
> To select between AHB and APB, a "dap apsel" command must be issued:
> dap apsel 0 -> following memory accesses are throuhg AHB
> dap apsel 1 -> following memory accesses are throuhg APB
Seems a weird usage of apsel. Could this be made more general, say a
command to set the memory access type (core, hostbus, etc). "dap
apsel 0" isn't very informative to users.
> @@ -1478,29 +1478,76 @@ static int cortex_a9_read_phys_memory(struct target
> *target,
Won't access via the core end up being translated by the MMU? IOW, is
this really a 'phys' access?
> + if ( apsel == 0) {
Use the "swjdp_memoryap" macro.
> + /* save registers r0 and r1, we are going to corrupt
> them */
> + retval = cortex_a9_dap_read_coreregister_u32(target,
> &saved_r0, 0);
> + if (retval != ERROR_OK)
> + return retval;
What if the core isn't halted?
Cheers,
-- Aaron
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