Signed-off-by: Luca Ellero <[email protected]>
---
src/target/arm_opcodes.h | 12 ++++++++++++
1 files changed, 12 insertions(+), 0 deletions(-)
mode change 100644 => 100755 src/target/arm_opcodes.h
diff --git a/src/target/arm_opcodes.h b/src/target/arm_opcodes.h
old mode 100644
new mode 100755
index b77721e..9a48e6d
--- a/src/target/arm_opcodes.h
+++ b/src/target/arm_opcodes.h
@@ -86,6 +86,12 @@
#define ARMV4_5_MSR_IM(Im, Rotate, Field, R) \
(0xe320f000 | (Im) | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
+/* Load Register Word Immediate Post-Index
+ * Rd: register to load
+ * Rn: base register
+ */
+#define ARMV4_5_LDRW_IP(Rd, Rn) (0xe4900004 | ((Rd) << 12) | ((Rn) <<
16))
+
/* Load Register Halfword Immediate Post-Index
* Rd: register to load
* Rn: base register
@@ -98,6 +104,12 @@
*/
#define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) <<
16))
+/* Store register Word Immediate Post-Index
+ * Rd: register to store
+ * Rn: base register
+ */
+#define ARMV4_5_STRW_IP(Rd, Rn) (0xe4800004 | ((Rd) << 12) | ((Rn) <<
16))
+
/* Store register Halfword Immediate Post-Index
* Rd: register to store
* Rn: base register
--
1.6.4.4
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