Hi, all:
For the TI OMAP3530 cortex a8, with an jtagkey like usb jtag tool, I can
debug it successfully.
But for hisilicon's cortex a9(not a8), it can recognize the core id but can't
halt it.
At omap3530.cfg I can see these lines:
proc omap3_dbginit {target} {
# General Cortex A8 debug initialisation
cortex_a8 dbginit
# Enable DBGU signal for OMAP353x
$target mww 0x5401d030 0x00002000
}
As its comments, I know before the omap3530 can be halted, must run the
command "$target mww 0x5401d030 0x00002000" to make it enter the debug
mode first. Omap3530 have two Debug Access Ports( MEM-AP AHB, MEM-AP APB), so
we can run "$target mww 0x5401d030 0x00002000"
before the core are halted, with MEM-AP AHB.
But for hisilicon's cortex a9, it has only one Debug Access Port (MEM-AP
APB), I don't know how to let it enter the debug mode. I can't halt
it when run "halt" command in the telnet window.
In hisilicon's configuration file, there are these lines:
proc hs_initdbg {target} {
echo "init debug.."
cortex_a8 dbginit
}
I think the "cortex_a8 dbginit" is not enough or is not complete to init the
cortex a8/a9.
The openocd I used is the latest development version.
The log for hisilicon:
> dap info 1
AP ID register 0x24770002
Type is MEM-AP APB
AP BASE 0x80000000
ROM table in legacy format
MEMTYPE System memory not present. Dedicated debug bus.
ROMTABLE[0x0] = 0x2003
Component base address 0x80002000, start address 0x80002000
Component class is 0x9, CoreSight component
Type is 0x14, Debug Control, Trigger Matrix
Peripheral ID[4..0] = hex 04 00 3b b9 06
Part is Coresight CTI (Cross Trigger)
ROMTABLE[0x4] = 0x3003
Component base address 0x80003000, start address 0x80003000
Component class is 0x9, CoreSight component
Type is 0x11, Trace Sink, Port
Peripheral ID[4..0] = hex 04 00 4b b9 12
Part is Coresight TPIU (Trace Port Interface Unit)
ROMTABLE[0x8] = 0x4003
Component base address 0x80004000, start address 0x80004000
Component class is 0x9, CoreSight component
Type is 0x12, Trace Link, Funnel, router
Peripheral ID[4..0] = hex 04 00 1b b9 08
Part is Coresight CSTF (Trace Funnel)
ROMTABLE[0xc] = 0x100003
Component base address 0x80100000, start address 0x80100000
Component class is 0x1, ROM table
Peripheral ID[4..0] = hex 04 00 0b b4 a9
Part is -*- unrecognized -*-
ROMTABLE[0x10] = 0x0
End of ROM table
dswei
[email protected]
2011-04-25
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