I know sw breakpoints w/cortex-a cpus need work to deal with cache and mmu handling.
Multi-core cortex a CPUs w/hardware and software breakpoints, especially when only halting a single CPU shoud be very interesting. -- Øyvind Harboe Can Zylin Consulting help on your project? US toll free 1-866-980-3434 / International +47 51 87 40 27 http://www.zylin.com/zy1000.html ARM7 ARM9 ARM11 XScale Cortex JTAG debugger and flash programmer _______________________________________________ Openocd-development mailing list [email protected] https://lists.berlios.de/mailman/listinfo/openocd-development
