Thanks! That's good to know.
I didn't realize that the STM32 can reset itself, too. That would be
problematic.
I suppose if I never use low power mode, I can omit both resets.
Matthew
On 7/22/2011 12:12 PM, Andreas Fritiofson wrote:
On Fri, Jul 8, 2011 at 1:19 AM, Matthew Lai <[email protected]
<mailto:[email protected]>> wrote:
Hello!
I'm trying to embed a FT2232D based programmer into my board with
a STM32 (Cortex-M3 MCU).
I want the programmer to be compatible with jtagkey, so I looked
at schematics of compaible designs.
I noticed that while the JTAG signals (TCK, TDI, TDO, TMS) are
only buffered when translation is necessary, the SRST and TRST
signals are always tri-state buffered, with OE going into the FTDI
chip.
Is there a reason for that? Can I omit the buffers?
Maybe you've already got the answers you needed, but a clarification
may be in order:
It's important that SRST is open-drain because it is a bidirectional
signal. The STM32 drives it low when it is reset internally. If it's
driven high, reset may not work and the chip may possibly even take
damage.
Also, I heard it's possible to omit the TRST signal and only keep
the SRST signal, because system reset will also reset the TAP
controller. Is that true? Are there problems with that?
TAP or debug logic is not reset by SRST, but you can skip TRST anyway
because TAP reset can be achieved by clocking in a pattern on TMS,
which OpenOCD does if no TRST is available. I'm not aware of any
problems, we have made several STM32 designs without TRST. Even the
SRST is optional, it can be asserted via debug logic, but it's good to
have because it may be the only way to reset the chip (other than POR)
if you're stuck in low power mode (JTAG unresponsive).
/Andreas
_______________________________________________
Openocd-development mailing list
[email protected]
https://lists.berlios.de/mailman/listinfo/openocd-development
