Hi,
inspired by this post, I created a reset-init script that initializes
the system clock for the STM32F107 (connectivity line) and sets the JTAG
speed to 6 MHz.
<https://lists.berlios.de/pipermail/openocd-development/2010-October/016709.html>
Currently, I source it in my custom configuration script, but it would
be nice to have this included into to the OpenOCD distribution.
source [find interface/arm-jtag-ew.cfg]
source [find board/olimex_stm32_h107.cfg]
source [find stm32f10x_cl_72MHz.cfg]
init
reset init
This JTAG speed yields flash programming at 13.6 kb/s, and stepping is
also pretty smooth.
Some further benchmarks (OpenOCD compiled without any additional logging):
@ 32 KHz: 1.9 kb/s
@ 64 KHz: 3.4 kb/s
@ 125 KHz: 5.6 kb/s
@ 250 KHz: 8.1 kb/s
@ 500 KHz: 10.2 kb/s
@ 1MHz: 11.8 kb/s
@ 2MHz: 12.9 kb/s
@ 4MHz: 13.4 kb/s
@ 6MHz: 13.6 kb/s
Next, I will try out the async. write patch mentioned here:
<https://lists.berlios.de/pipermail/openocd-development/2011-July/020261.html>
(and related posts).
Best regards,
Simon
# Enable PLL2 and PLL (as in CMSIS system_stm32f10x.c)
# and clock system with 72 Mhz
#
# Set JTAG clock to 6 MHz
$_TARGETNAME configure -event reset-init {
# RCC_CR reset value: 0x??83
# RCC_CR -> RCC_CR_HSEON
mww 0x40021000 0x10083
sleep 10
# FLASH_ACR reset value: 0x30
# FLASH_ACR -> FLASH_ACR_PRFTBE, FLASH_ACR_LATENCY_2
mww 0x40022000 0x32
# RCC_CFGR reset value: 0x0
# RCC_CFGR -> RCC_CFGR_HPRE_DIV1, RCC_CFGR_PPRE2_DIV1,
RCC_CFGR_PPRE1_DIV2
mww 0x40021004 0x400
# RCC_CFGR2 reset value: 0x0
# RCC_CFGR2 -> RCC_CFGR2_PREDIV2_DIV5, RCC_CFGR2_PLL2MUL8,
# RCC_CFGR2_PREDIV1SRC_PLL2, RCC_CFGR2_PREDIV1_DIV5
mww 0x4002102c 0x10644
# RCC_CR -> RCC_CR_PLL2ON
mww 0x40021000 0x4010083
sleep 10
# RCC_CFGR -> PLLCLK = PREDIV1 * 9 = 72 MHz
mww 0x40021004 0x1d0400
# RCC_CR -> RCC_CR_PLLON
mww 0x40021000 0x5010083
sleep 10
# RCC_CR -> RCC_CFGR_SW_PLL
mww 0x40021004 0x1d0402
sleep 10
adapter_khz 6000
}
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