Additional information: I think the jlink can not communicate with my CPU msm7x27A (when CPU is in the reset state) Because now, the "reset" and "halt" command is working. But the "reset halt" and "reset init" isn't. When execute "reset halt", it will display some errors: > reset halt JTAG tap: msm7xxx.cpu tap/device found: 0x006300e1 (mfg: 0x070, part: 0x0630, ver: 0x0) WARNING: unknown debug reason: 0xf jlink_usb_message failed with result=5) jlink_tap_execute, wrong result -107 (expected 270)
According to the User Guide: In the best case, OpenOCD can hold SRST, then reset the TAPs via TRST and send commands through JTAG to halt the CPU at the reset vector before the 1st instruction is executed. Then when it finally releases the SRST signal, the system is halted under debugger control before any code has executed. This is the behavior required to support the reset halt and reset init commands; after reset init a board-specific script might do things like setting up DRAM. Thanks a lot in advance. Best Regards Richard LIU On Thu, Aug 4, 2011 at 4:37 PM, Liu Hua <[email protected]> wrote: > Hi, > > I am a newbie of openocd. I am using JLink to debug a ARM926ejs CPU. > During startup of openocd, it will use EMU_CMD_GET_STATE command to get all > the pins state of jlink. > > On a working board, it gets TMS = 0 SRST = 0 TRST = 0 > On a no-working board, it gets TMS = 0 SRST = 1 TRST = 0, (then it will > get the wrong message: Error: jlink_usb_message failed with result=5) > > In my understanding, when SRST is low, the system will reset. I think it > should be high at the startup time. > But, why when SRST=0, the JTAG works? > > Best Regards > Richard LIU > > > > >
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