Hi,
I'm having lots of problems with this Toradex board.
I use a custom carrier board without JTAG buffers, so I connected my
JTAG-USB directly to the Colibri FFC JTAG connector. My JTAG adapter is
FT2232 based and uses the OOCDLink layout, which means it has NTRST and
NSRST buffers with OE. I traced all the signals from the Colibri board
to the JTAG adapters, everything looks ok. I looked at the signals with
an (analogue) oscilloscope and saw the reset signals and pulses on TMS,
TCK, TDI and TDO.
However, here is what I get:
OpenOCD startup:
Open On-Chip Debugger 0.6.0-dev-00079-g4017af8-dirty (2011-09-11-23:08)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.berlios.de/doc/doxygen/bugs.html
Info : only one transport option; autoselect 'jtag'
100 kHz
adapter_nsrst_delay: 260
jtag_ntrst_delay: 250
Info : colibri_pxa320.cpu: hardware has 2 breakpoints and 2 watchpoints
trst_and_srst separate srst_gates_jtag trst_push_pull srst_open_drain
adapter_nsrst_delay: 800
Info : clock speed 100 kHz
Info : JTAG tap: colibri_pxa320.cpu tap/device found: 0x7e642013 (mfg: 0x009,
part: 0xe642, ver: 0x7)
Trying to halt the CPU:
reset halt
JTAG tap: colibri_pxa320.cpu tap/device found: 0x7e642013 (mfg: 0x009, part:
0xe642, ver: 0x7)
Bad value '00' captured during DR or IR scan:
check_value: 0x02
check_mask: 0x07
JTAG error while writing DCSR
Bad value '00' captured during DR or IR scan:
check_value: 0x02
check_mask: 0x06
JTAG error while reading TX
error while polling TX register, reset CPU
target state: halted
target halted in ARM state due to undefined, current mode: User
cpsr: 0x00000000 pc: 0x00000000
MMU: disabled, D-Cache: disabled, I-Cache: disabled
When I try to resume, I get lots of those "Bad value '00' captured..."
messages and eventually a "time out writing RX register".
Strangely, when I change my reset configuration to "reset_config none",
the behaviour changes a bit:
reset halt
JTAG tap: colibri_pxa320.cpu tap/device found: 0x7e642013 (mfg: 0x009, part:
0xe642, ver: 0x7)
BUG: can't assert SRST
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x280000d3 pc: 0x00000000
MMU: disabled, D-Cache: disabled, I-Cache: disabled
(processor reset)
resume 0xc5040000
Failed to receiving data from debug handler after 1000 attempts
in procedure 'resume'
I am wondering why OpenOCD is perfectly able to find the TAP and read
some CPU registers at startup, while it obviously fails to clock in TDO
correctly afterwards.
I tried different reset configurations and timing settings, even down to
1 kHz, without success. After reading some posts about possibly too low
drive strength of the FT2232, I added a simple 74HC125 buffer for TMS,
TDI, TDO and TCK. Unfortunately, this didn't help either.
Any suggestions?
Best regards,
Oliver
_______________________________________________
Openocd-development mailing list
[email protected]
https://lists.berlios.de/mailman/listinfo/openocd-development
