> Dmitry E. Oboukhov wrote: >> I cant upload an image into internal SRAM (AT91SAM9). >> it can really write only 20 bytes. >> load_image into internal flash area works fine.
> Are you using latest openocd git code, if not which version?
I'm using the latest openocd release (0.5.0/Debian)
> Perhaps this is a problem of clocking, OpenOCD may need to set that
> up depending on what the chip expects.
> Which JTAG speed are you using? It should say in the output from
> running openocd.
I'm using SAM-ICE (Segger) device with settings like openocd
doc/examples.
Open On-Chip Debugger 0.5.0 (2011-08-09-08:45)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.berlios.de/doc/doxygen/bugs.html
Warn : Adapter driver 'jlink' did not declare which transports it allows;
assuming legacy JTAG-only
Info : only one transport option; autoselect 'jtag'
trst_and_srst separate srst_gates_jtag trst_push_pull srst_open_drain
adapter_nsrst_delay: 300
jtag_ntrst_delay: 200
RCLK - adaptive
dcc downloads are enabled
fast memory access is enabled
Info : J-Link initialization started / target CPU reset initiated
Info : J-Link ARM V8 compiled Mar 27 2009 16:41:15
Info : J-Link caps 0x39ff7bbf
Info : J-Link hw version 80000
Info : J-Link hw type J-Link
Info : J-Link max mem block 9744
Info : J-Link configuration
Info : USB-Address: 0xff
Info : Kickstart power on JTAG-pin 19: 0xffffffff
Info : Vref = 2.426 TCK = 1 TDI = 0 TDO = 0 TMS = 0 SRST = 0 TRST = 0
Info : J-Link JTAG Interface ready
Info : RCLK (adaptive clock speed)
Info : JTAG tap: at91sam9xe512.tap tap/device found: 0x0792603f (mfg: 0x01f,
part: 0x7926, ver: 0x0)
Info : Embedded ICE version 6
Info : at91sam9xe512.target: hardware has 2 breakpoint/watchpoint units
Info : JTAG tap: at91sam9xe512.tap tap/device found: 0x0792603f (mfg: 0x01f,
part: 0x7926, ver: 0x0)
target state: halted
target halted in ARM state due to breakpoint, current mode: Supervisor
cpsr: 0x000000d3 pc: 0x00000000
MMU: disabled, D-Cache: disabled, I-Cache: disabled
dcc downloads are enabled
Loading loader...
load_image /home/unera/invertor/obj/wblock.bin 0x300000 bin
Error: DCC write failed, expected end address 0x0030060c got 0x300014
Runtime Error: arm-lib/openocd/at91sam9xe-flash.tcl:181:
in procedure 'script'
at file "embedded:startup.tcl", line 58
in procedure 'ecc_write_image_bl' called at file "obj/oo.prog.cfg", line 3
in procedure 'load_image' called at file
"arm-lib/openocd/at91sam9xe-flash.tcl", line 181
> General suggestions would be to disable DCC and to try lower JTAG
> speed, but at best those are workarounds. The real solution is
> probably more complicated.
But why it doesn't fail if it writes the other regions?
It crashes only if it writes into internal SRAM.
I used openocd to program internal flash using algorithm like:
1. write 512 bytes (load_image) into flash
2. touch flash registers to start writting
3. repeat 1 with the other 512-block
Then I wanted to debug programs from SRAM, so I'be built a test and
tried to upload it into SRAM and found the problem :(
--
. ''`. Dmitry E. Oboukhov
: :’ : email: [email protected] jabber://[email protected]
`. `~’ GPGKey: 1024D / F8E26537 2006-11-21
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