On 09/29/2011 09:40 AM, Michel JAOUEN wrote:
Hello,
I implemented the flush of L1 and L2 cache for cortex_a.
I added the support of phys memory access through dap apsel 1,
(for this access, a flush is performed, and mmu is disabled)
I also implement va_to_pa mechanism for virt_to_phys.
For that purpose, I have modified the architecture :
Instead of increasing cortex_a.c file, I moved this new support
feature to armv7a.c .
The reason of this change is to prepare later cortex_a evolution.(A15,
A7), that could be implemented in
Another file than cortex_a.c relying on a set of function from amv7a file.
Best Regards.
Michel JAOUEN
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Michel,
I am trying to understand what the "cache_config" command does so that I
can add this functionality to the Pandaboard. I apologize for the list
of questions, but the operation is not clear and I didn't see any
documentation for this feature:
* Is the address supposed to point to the base PL310 address?
* Why do you call this operation if the target status is unknown?
* What does this operation do when called?
I appreciate any insight you can provide.
Thanks,
Karl
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