Using OpenOCD on TI DM365, something goes wrong when trying to enable extra TAPs using the JRC; it claims they are enabled, but has trouble getting the version of the EmbeddedICE, and the "halt" command times out and doesn't work.
If I set the EMU0/1 pins so that the extra TAPs are always routed in, then things work OK. I have previously used OpenOCD with DM355, the predecessor SoC, which had the same TAP enable by JRC scheme (which works fine). Any clues on this? I think David Brownell would have been the guy. Good output with TAPs fixed as enabled (EMU pins low): Open On-Chip Debugger 0.6.0-dev-00128-g36e3009-dirty (2011-10-19-20:05) ... trst_only separate trst_push_pull CS0 NAND Info : RCLK (adaptive clock speed) not supported - fallback to 1500 kHz Info : JTAG tap: dm365.etb tap/device found: 0x2b900f0f (mfg: 0x787, part: 0xb900, ver: 0x2) Info : JTAG tap: dm365.arm tap/device found: 0x0792602f (mfg: 0x017, part: 0x7926, ver: 0x0) Info : JTAG tap: dm365.jrc tap/device found: 0x0b83e02f (mfg: 0x017, part: 0xb83e, ver: 0x0) Info : Embedded ICE version 6 Info : dm365.arm: hardware has 2 breakpoint/watchpoint units Info : ETM v1.3 > halt target state: halted target halted in ARM state due to debug-request, current mode: Supervisor cpsr: 0x800000d3 pc: 0x0000b888 MMU: disabled, D-Cache: disabled, I-Cache: disabled --- Bad output with EMU pins high (default) Open On-Chip Debugger 0.6.0-dev-00128-g36e3009-dirty (2011-10-19-20:05) ... trst_only separate trst_push_pull CS0 NAND Info : RCLK (adaptive clock speed) not supported - fallback to 1500 kHz Info : JTAG tap: dm365.jrc tap/device found: 0x0b83e02f (mfg: 0x017, part: 0xb83e, ver: 0x0) Info : JTAG tap: dm365.etb enabled Info : JTAG tap: dm365.arm enabled Info : Embedded ICE version 0 Error: unknown EmbeddedICE version (comms ctrl: 0x00000000) Info : dm365.arm: hardware has 2 breakpoint/watchpoint units Info : ETM v1.0 > halt Info : Halt timed out, wake up GDB. Error: timed out while waiting for target halted in procedure 'halt' Holding the EMU pins low is a possibility but means PCB mods to our board, so it would be nice to get this working.. Happy to hack and submit a patch if someone can give me clues to get started. -- Jon Povey jon.po...@racelogic.co.uk Racelogic is a limited company registered in England. Registered number 2743719 . Registered Office Unit 10, Swan Business Centre, Osier Way, Buckingham, Bucks, MK18 1TB . The information contained in this electronic mail transmission is intended by Racelogic Ltd for the use of the named individual or entity to which it is directed and may contain information that is confidential or privileged. If you have received this electronic mail transmission in error, please delete it from your system without copying or forwarding it, and notify the sender of the error by reply email so that the sender's address records can be corrected. The views expressed by the sender of this communication do not necessarily represent those of Racelogic Ltd. Please note that Racelogic reserves the right to monitor e-mail communications passing through its network _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
