Hello,
i have append my experimental config files for the ti tms570 usb eval board.
Flash is not supported
by openocd yet. Maybe its useful for someone.
> flash info 0
device_ident_reg = 0x80206d0d
Could not identify part 0x21 as a member of the TMS470 family.
auto_probe failed
in procedure 'flash'
Regards,
Mathias
#
# TMS570 Microcontroller USB Kit
# http://www.ti.com/tool/tmdx570ls20susb
#
source [find interface/xds100v2.cfg]
set CHIPNAME tms570ls
adapter_khz 10
source [find target/ti_tms570ls.cfg]
#
# TI TMS570LS
#
###############################################################################
# User modifiable parameters
###############################################################################
set _ENDIAN big
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME tms570ls
}
set _JRC_TAPID 0x1b7b302f
# Run the adapter at the fastest acceptable speed with the slowest possible
# core clock.
adapter_khz 100
###############################################################################
# JTAG setup
# The OpenOCD commands are described in the TAP Declaration section
# http://openocd.berlios.de/doc/html/TAP-Declaration.html
###############################################################################
source [find target/icepick.cfg]
# The TAP order should be described from the TDO connection in OpenOCD to the
# TDI pin. The OpenOCD FAQ describes this in more detail:
# http://openocd.berlios.de/doc/html/FAQ.html
# From SPRUGN4B CH27 the available secondary TAPs are in this order from TDO:
#
# Device | TAP number
# ---------|------------
# DAP | 3
# Sequencer| 2 Note: The sequencer is an ARM968
# DSP | 1
# D2D | 0
#
# Right now the only secondary tap enabled is the DAP so the rest are left
# undescribed.
######
# Start of Chain Description
# The Secondary TAPs all have enable functions defined for use with the ICEpick
# Only the DAP is enabled. The AM37xx does not have the Sequencer or DSP but
# the TAP numbers for ICEpick do not change.
#
# TODO: A disable function should also be added.
######
# Secondary TAP: D2D it is not in the chain by default (-disable)
# The ICEpick can be used to enable it in the chain.
# This IRLEN is probably incorrect - not sure where the documentation is.
jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0x0f -disable
jtag configure $_CHIPNAME.etb -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 1"
# Secondary TAP: DAP is closest to the TDO output
# The TAP enable event also needs to be described
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0x1 -disable
jtag configure $_CHIPNAME.dap -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 0"
# Primary TAP: ICEpick - it is closest to TDI so last in the chain
jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
-expected-id $_JRC_TAPID
######
# End of Chain Description
######
######
# Start JTAG TAP events
######
# some TCK tycles are required to activate the DEBUG power domain
jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
# Enable the DAP TAP
jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
######
# End JTAG TAP events
######
###############################################################################
# Target Setup:
# This section is described in the OpenOCD documentation under CPU Configuration
# http://openocd.berlios.de/doc/html/CPU-Configuration.html
###############################################################################
# Create the CPU target to be used with GDB: Cortex-A8, using DAP
set _TARGETNAME $_CHIPNAME.dap
target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap
# -variant arm1176
# The DM37x has 64K of SRAM starting at address 0x4020_0000. Allow the first
# 16K to be used as a scratchpad for OpenOCD.
#$_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
# size is automatically "calculated" by probing
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME tms470 0x000000000 0x00200000 1 1 $_TARGETNAME
###############################################################################
# Target Functions
# Add any functions needed for the target here
###############################################################################
# Run this to enable invasive debugging. This is run automatically in the
# reset sequence.
proc amdm37x_dbginit {target} {
# # General Cortex A8 debug initialisation
cortex_a8 dbginit
# Enable DBGEN signal. This signal is described in the ARM v7 TRM, but
# access to the signal appears to be implementation specific. TI does not
# describe this register much except a quick line that states DBGEM (sic) is
# at this address and this bit.
# $target mww phys 0x5401d030 0x00002000
}
#jtag_rclk 100
#etm config $_TARGETNAME 16 normal half etb
#etb config $_TARGETNAME $_CHIPNAME.etb
######
# Start Target Reset Event Setup:
######
# Set the JTAG clock down to 10 kHz to be sure that it will work with the
# slowest possible core clock (16.8MHz/2 = 8.4MHz). It is OK to speed up
# *after* PLL and clock tree setup.
$_TARGETNAME configure -event "reset-start" { adapter_khz 10 }
# Describe the reset assert process for openocd - this is asserted with the
# ICEPick
$_TARGETNAME configure -event "reset-assert" {
global _CHIPNAME
# assert warm system reset through ICEPick
icepick_c_wreset $_CHIPNAME.jrc
}
# After the reset is asserted we need to re-initialize debugging and speed up
# the JTAG clock.
$_TARGETNAME configure -event reset-assert-post {
global _TARGETNAME
amdm37x_dbginit $_TARGETNAME
adapter_khz 1000
}
$_TARGETNAME configure -event gdb-attach {
global _TARGETNAME
amdm37x_dbginit $_TARGETNAME
echo "Halting target"
halt
}
######
# End Target Reset Event Setup:
######
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