Hi, I bought the new ordb2a-ep4ce22 and now I have finally some time to play with (work on) it. The first steps went well but now I have problems going further with RTL development.
I plan to port my 1-wire master and SPI (dual/quad) master to the board, so I will have to edit the RTL, simulate, synthesize and later write Linux drivers (with help from a friend). The steps from Get_Started.txt and Running_SW_on_FPGA_board.txt went well, I was able to load the FPGA, load the linux image over GDB, logint into Linux, connect ethernet, ping around. I did not try to load the SPI flash. Another thing I was able to do without much trouble was FPGA synthesis with Quartus. There were some problems installing Quartus on Ubuntu (I did not install into the virtual image I do not have enough RAM for this). The steps I had to take were something like this: 1. download Quartus web edition 2. start a terminal and: $ cd Downloads $ sh 11.1_173_quartus_free_linux.sh # setup fails to run $ cd 11.1_173_quartus_free_linux $ sudo bash setup 3. repeat for service pack 3. run Quartus and open project orpsocv2/boards/altera/ordb2a-ep4ce22/syn/quartus/ORDB2A.qpf 4. try to compile, there was a difference between the old and new megacore libraries, comment out a line in a source file (look at errors) 5. loaded the board and connected to the monitor over USB/UART Then things stopped going fluently, I hope somebody helps me or at least places my complaints on a TODO list. I will be able to continue by myself, but slowly. I will describe the next issues: 1. no ordb2a-ep4ce22 simulation environment out of the box 2. no update path, version control support, 3. no way to be sure what is loaded into the FPGA 4. outdated Verilog tools 1. no ordb2a-ep4ce22 simulation environment out of the box ----------------------------------------------------------------------------- A simulation environment for the root top design is available but there is no environment for the board itself, by default it is configured to Modelsim, which is not installed. 2. no update path, version control support, reference repository --------------------------------------------------------------------------------- The RTL, bench source directories are without a link to SVN/GIT repositories. I was also not able to find such repositories online. The ordb2a-ep4ce22 repo is nowhere to be found! If I would like to make a patch for RTL/bench/environment I would have to first create a git repository (which is simple). There is also no way to update to the latest master, loading a new ISO image is not a good update path. A simple way to fix this would be to use a git clone of the main repo, with only read permissions, the user would be later able to change git setting or just use the repo for local commits. It would also be possible to update to master. I think most of you would agree that new users should be helped with learning version control tools from the beginning. The best option for me would be to make a form on github. 3. no way to be sure what is loaded into the FPGA ----------------------------------------------------------------- Usually FPGA boards have a programmable pin driven LED, so there is always a way to check if programming went right by writing some blinkenlights RTL. I do not know, if it is possible to use Altera toos to access the board. For example to read the programmable ID, verify programming, use SignalTap, ... I was not able to identify the build from the monitor, an RTL hard coded version register displayed by the monitor would help. 4. outdated Verilog tools ------------------------------- This is not a big issue. The iverilog, gtkwave versions are outdated and verilator is not installed. The latest versions of this software can be copied from my PPA to an OpenCores PPA. https://launchpad.net/~team-electronics/+archive/ppa Verilator is without SystemC support, due to licensing issues (permission to distribute SystemC is not granted). If somebody is interested into my SPI/dual/quad code, here it is: https://github.com/jeras/sockit_spi Regards, Iztok Jeras _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
