This will silence a few compiler warnings
Index: or1200/core/rtl/verilog/or1200_wb_biu.v
===================================================================
--- or1200.orig/core/rtl/verilog/or1200_wb_biu.v 2012-02-14
22:02:45.694655518 +0100
+++ or1200/core/rtl/verilog/or1200_wb_biu.v 2012-02-14 22:03:30.330657467
+0100
@@ -175,9 +175,9 @@
reg [1:0] wb_fsm_state_cur; // WB FSM -
surrent state
reg [1:0] wb_fsm_state_nxt; // WB FSM -
next state
- wire [1:0] wb_fsm_idle = 2'h0; // WB FSM state
- IDLE
- wire [1:0] wb_fsm_trans = 2'h1; // WB FSM state
- normal TRANSFER
- wire [1:0] wb_fsm_last = 2'h2; // EB FSM state
- LAST transfer
+ localparam wb_fsm_idle = 2'h0; // WB FSM state
- IDLE
+ localparam wb_fsm_trans = 2'h1; // WB FSM state
- normal TRANSFER
+ localparam wb_fsm_last = 2'h2; // EB FSM state
- LAST transfer
--
Olof Kindgren
______________________________________________
ORSoC
Website: www.orsoc.se
Email: [email protected]
______________________________________________
FPGA, ASIC, DSP - embedded SoC design
_______________________________________________
OpenRISC mailing list
[email protected]
http://lists.openrisc.net/listinfo/openrisc
