2012/2/22 Stefan Strålsjö <[email protected]>: > Hi all, > > [email protected] > > I'm trying to introduce a way to align the IP header so it starts on a 32 bit > word. This when using the DMA function so that the stored word is aligned in > RAM. > > Today we have this : > > ----------------- <- Byte 0 > | MAC header | > | 14 bytes | > ----------------- <- Byte 14 (NOT word aligned: problematic) > | IP header | > ----------------- > | Data | > ----------------- > | Unused | > ----------------- <- Byte 1536 (I think...) > > I'm using the ethmac fr OC (Igor Mohors). Latest version. > > So I' have added a bit to align in eth_registers.v meaning the following: > > ----------------- <- Byte 0 > | 2 empty bytes | > ----------------- > | MAC header | > | 14 bytes | > ----------------- <- Byte 16 (word aligned, this is the what we want) > | IP header | > ----------------- > | Data | > ----------------- > | Unused | > ----------------- <- Byte 1538 (I think...) > > In the eth_wishbone.v > > RxStartFrm indicates start of frame. RxbyteSel indicates active bytes in the > word. > > My question is if I can insert 2 dummy bytes to align the by manipulating the > insert of data with the RXPointerLSB_rst and RxBytecnt to add these tvo extra > "dummy" bytes. > > Regards > Stefan > _______________________________________________ > OpenRISC mailing list > [email protected] > http://lists.openrisc.net/listinfo/openrisc
Hi Stefan, This has been on my todo-list for quite some time. There are a few ways to do this, and what you propose is the simplest solution. In that case, I would propose that a flag is added to the register map to turn it on and off. Unfortunately eth_wishbone.v is a mess and has some shady CDC problems. I've been intending to rewrite the whole thing, but haven't had time so patches are most welcome. -- Olof Kindgren ______________________________________________ ORSoC Website: www.orsoc.se Email: [email protected] ______________________________________________ FPGA, ASIC, DSP - embedded SoC design _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
