Adding [email protected] and [email protected]
> From: [email protected] > Date: Mon, 27 Feb 2012 18:03:30 +0000 > Subject: Re: A typo error on latest openrisc_arch_draft.odt > To: [email protected] > > On Mon, Feb 27, 2012 at 5:27 PM, XueBrian <[email protected]> wrote: > > Hi Julius, > > > > > > In section 4.7 PCMRx[SUMRA] should be SR[SUMRA]? > > > > 4.7 Exception Program Counter Registers (EPCR0 - EPCR15) > > > > The Exception Program Counter registers are special-purpose supervisor-level > > registers accessible with the l.mtspr/l.mfspr instructions in supervisor > > mode. Read access in user mode is possible if it is enabled in PCMRx[SUMRA]. > > They are 32-bit wide registers in 32-bit implementations and can be wider > > than 32 bits in 64-bit implementations. > > > > > > Hi Brian, > > Thanks for the suggestion. I think you're probably right. > > But could you please submit this to the openrisc mailing lists: > > [email protected] and [email protected] > > Thanks > > Julius
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