2012/3/9 Ouabache Designworks <[email protected]>: > > Franck, > > What you are dealing with is somewhat of a mess caused by the original > debugger. Jtag needs a lockup latch on tdo in order the deal with clock > skew. The original debugger and its tap decided to put this on the output of > each register and the tdo is then simply muxed out to the pad. The > adv_debug_system and most of the rest of the world does not put the lockup > latch on each register but rather puts one latch on the output of the mux > before it goes out to the pad. > > What your are seeing is that if both the register and the tap each add a > lockup latch then it doesn't work. Your fix removes the latch from the > register so it can work with the fpgas tap. > > > Your fix will break the debugger if you try to use it with it's original > tap. It will work with the adv_debug_system tap. >
So we should fix the original tap controller to match the vjtag (usual ?) behavior, then fix the or_dbg_proxy (is it its name ? still supported ?) . Agree ? > > The original debugger also uses the pause_dr state for something and this > can be a problem since not all fpga taps deliver this state. There is also > and issue in that some taps deliver a capture_dr clock while others deliver > a capture_dr enable signal. We should make our debuggers work with either > one. > > > John Eaton > What do you suggest for the future ? I'm not a JTAG expert so if you have a plan to get a reliable solution please enumerate your plan steps :) I can't investigate on the original tap because I don't have a board with two JTAG on it. Thanks for your help. Franck. _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
