Hallo Jeremy:
[...]
We recognized some time ago that the solution is that almost all the C
tests should use plain newlib. You really only need a custom bootloader
for the assembler tests, and possibly the exception handling tests.
It is a good idea to run the tests with a range of starting conditions,
but remember that slows Or1ksim (you have to initialize the memory), so
the tests will take longer. IIRC Or1ksim by default doesn't actively
initialize memory to zero, it just uses whatever is there.
Until or1ksim's test suite gets moved over to newlib, please find
attached to this message a patch to clear the BSS section in all
test-code-or1k test cases.
I have also changed the configured memory type for all those simulations
to "exitnops". That should help catch quickly any new test cases that
don't initialise BSS properly.
There is one thing I forgot in the patch though, you have to add
EXTRA_DIST = support.inc
to
testsuite/test-code-or1k/support/Makefile.am
Thanks,
Ruben
Index: testsuite/or1ksim.tests/acv-gpio.cfg
===================================================================
--- testsuite/or1ksim.tests/acv-gpio.cfg (revision 787)
+++ testsuite/or1ksim.tests/acv-gpio.cfg (working copy)
@@ -1,9 +1,5 @@
section memory
- /*random_seed = 12345
- type = random*/
- pattern = 0x00
- type = unknown /* Fastest */
-
+ type = exitnops
name = "RAM"
ce = 1
baseaddr = 0x00000000
@@ -13,11 +9,7 @@
end
section memory
- /*random_seed = 12345
- type = random*/
- pattern = 0x00
- type = unknown /* Fastest */
-
+ type = exitnops
name = "FLASH"
ce = 0
baseaddr = 0xf0000000
Index: testsuite/or1ksim.tests/acv-uart.cfg
===================================================================
--- testsuite/or1ksim.tests/acv-uart.cfg (revision 787)
+++ testsuite/or1ksim.tests/acv-uart.cfg (working copy)
@@ -1,8 +1,5 @@
section memory
- /*random_seed = 12345
- type = random*/
- pattern = 0x00
- type = unknown /* Fastest */
+ type = exitnops
name = "FLASH"
ce = 0
@@ -13,10 +10,7 @@
end
section memory
- /*random_seed = 12345
- type = random*/
- pattern = 0x00
- type = unknown /* Fastest */
+ type = exitnops
name = "RAM"
ce = 1
Index: testsuite/or1ksim.tests/default.cfg
===================================================================
--- testsuite/or1ksim.tests/default.cfg (revision 787)
+++ testsuite/or1ksim.tests/default.cfg (working copy)
@@ -22,11 +22,8 @@
with this program. If not, see <http: www.gnu.org/licenses/>. */
section memory
- /*random_seed = 12345
- type = random*/
- pattern = 0x00
- type = unknown /* Fastest */
-
+ /* This is OK for the JTAG tests */
+ type = exitnops
name = "FLASH"
ce = 0
mc = 0
@@ -37,11 +34,7 @@
end
section memory
- /*random_seed = 12345
- type = random*/
- pattern = 0x00
- type = unknown /* Fastest */
-
+ type = exitnops
name = "RAM"
ce = 1
mc = 0
Index: testsuite/or1ksim.tests/eth.cfg
===================================================================
--- testsuite/or1ksim.tests/eth.cfg (revision 787)
+++ testsuite/or1ksim.tests/eth.cfg (working copy)
@@ -22,11 +22,7 @@
with this program. If not, see <http: www.gnu.org/licenses/>. */
section memory
- /*random_seed = 12345
- type = random*/
- pattern = 0x00
- type = unknown /* Fastest */
-
+ type = exitnops
name = "FLASH"
ce = 0
mc = 0
@@ -37,11 +33,7 @@
end
section memory
- /*random_seed = 12345
- type = random*/
- pattern = 0x00
- type = unknown /* Fastest */
-
+ type = exitnops
name = "RAM"
ce = 1
mc = 0
Index: testsuite/or1ksim.tests/fp.cfg
===================================================================
--- testsuite/or1ksim.tests/fp.cfg (revision 787)
+++ testsuite/or1ksim.tests/fp.cfg (working copy)
@@ -22,11 +22,7 @@
with this program. If not, see <http: www.gnu.org/licenses/>. */
section memory
- /*random_seed = 12345
- type = random*/
- pattern = 0x00
- type = unknown /* Fastest */
-
+ type = exitnops
name = "FLASH"
ce = 0
mc = 0
@@ -37,11 +33,7 @@
end
section memory
- /*random_seed = 12345
- type = random*/
- pattern = 0x00
- type = unknown /* Fastest */
-
+ type = exitnops
name = "RAM"
ce = 1
mc = 0
Index: testsuite/or1ksim.tests/inst-set-test.cfg
===================================================================
--- testsuite/or1ksim.tests/inst-set-test.cfg (revision 787)
+++ testsuite/or1ksim.tests/inst-set-test.cfg (working copy)
@@ -26,7 +26,7 @@
or flash memory. */
section memory
- type = unknown /* Fastest */
+ type = exitnops
name = "RAM"
baseaddr = 0x00000000
size = 0x00200000
Index: testsuite/or1ksim.tests/kbdtest.cfg
===================================================================
--- testsuite/or1ksim.tests/kbdtest.cfg (revision 787)
+++ testsuite/or1ksim.tests/kbdtest.cfg (working copy)
@@ -22,10 +22,7 @@
with this program. If not, see <http: www.gnu.org/licenses/>. */
section memory
- /*random_seed = 12345
- type = random*/
- pattern = 0x00
- type = unknown /* Fastest */
+ type = exitnops
name = "FLASH"
ce = 0
@@ -37,10 +34,7 @@
end
section memory
- /*random_seed = 12345
- type = random*/
- pattern = 0x00
- type = unknown /* Fastest */
+ type = exitnops
name = "RAM"
ce = 1
Index: testsuite/or1ksim.tests/mmu.cfg
===================================================================
--- testsuite/or1ksim.tests/mmu.cfg (revision 787)
+++ testsuite/or1ksim.tests/mmu.cfg (working copy)
@@ -22,11 +22,7 @@
with this program. If not, see <http: www.gnu.org/licenses/>. */
section memory
- /*random_seed = 12345
- type = random*/
- pattern = 0x00
- type = unknown /* Fastest */
-
+ type = exitnops
name = "RAM"
ce = 1
baseaddr = 0x00000000
@@ -36,11 +32,7 @@
end
section memory
- /*random_seed = 12345
- type = random*/
- pattern = 0x00
- type = unknown /* Fastest */
-
+ type = exitnops
name = "FLASH"
ce = 0
baseaddr = 0xf0000000
Index: testsuite/or1ksim.tests/pcu.cfg
===================================================================
--- testsuite/or1ksim.tests/pcu.cfg (revision 787)
+++ testsuite/or1ksim.tests/pcu.cfg (working copy)
@@ -23,11 +23,7 @@
with this program. If not, see <http: www.gnu.org/licenses/>. */
section memory
- /*random_seed = 12345
- type = random*/
- pattern = 0x00
- type = unknown /* Fastest */
-
+ type = exitnops
name = "RAM"
ce = 1
mc = 0
Index: testsuite/test-code-or1k/cache/cache-asm.S
===================================================================
--- testsuite/test-code-or1k/cache/cache-asm.S (revision 787)
+++ testsuite/test-code-or1k/cache/cache-asm.S (working copy)
@@ -26,6 +26,7 @@
--------------------------------------------------------------------------*/
#include "spr-defs.h"
+#include "support.inc"
#include "board.h"
#define IC_ENABLE 0
@@ -93,7 +94,9 @@
l.movhi r1,hi(stack)
l.ori r1,r1,lo(stack)
l.ori r2,r1, 0
-
+
+ CLEAR_BSS
+
l.movhi r3,hi(main)
l.ori r3,r3,lo(main)
l.jr r3
Index: testsuite/test-code-or1k/cache/cache.ld
===================================================================
--- testsuite/test-code-or1k/cache/cache.ld (revision 787)
+++ testsuite/test-code-or1k/cache/cache.ld (working copy)
@@ -55,10 +55,25 @@
*(.rodata.*)
_dst_end = .;
} > ram
- .bss :
+
+
+ .bss :
{
*(.bss)
+
+ /* WARNING about section size alignment:
+ The start-up assembly code can only clear BSS section sizes which
are aligned to 4 bytes.
+ However, the size of the BSS section may not be aligned, therefore
up to 3 bytes more
+ could be zeroed on start-up. This is normally not an issue, as the
start of the next section
+ is usually aligned too, so those extra bytes should be just
padding. I did try the following
+ trick to align the BSS section size, to no avail:
+ . = ALIGN(., 4); */
} > ram
+
+ _bstart = ADDR(.bss);
+ _bend = _bstart + SIZEOF(.bss);
+
+
.stack ALIGN(0x10) (NOLOAD):
{
*(.stack)
Index: testsuite/test-code-or1k/default.ld
===================================================================
--- testsuite/test-code-or1k/default.ld (revision 787)
+++ testsuite/test-code-or1k/default.ld (working copy)
@@ -62,13 +62,24 @@
_dst_end = .;
} > ram
+
.bss :
{
- _bstart = .;
*(.bss)
- _bend = .;
+
+ /* WARNING about section size alignment:
+ The start-up assembly code can only clear BSS section sizes which
are aligned to 4 bytes.
+ However, the size of the BSS section may not be aligned, therefore
up to 3 bytes more
+ could be zeroed on start-up. This is normally not an issue, as the
start of the next section
+ is usually aligned too, so those extra bytes should be just
padding. I did try the following
+ trick to align the BSS section size, to no avail:
+ . = ALIGN(., 4); */
} > ram
+ _bstart = ADDR(.bss);
+ _bend = _bstart + SIZEOF(.bss);
+
+
.stack ALIGN(0x10) (NOLOAD):
{
*(.stack)
Index: testsuite/test-code-or1k/except-mc.ld
===================================================================
--- testsuite/test-code-or1k/except-mc.ld (revision 787)
+++ testsuite/test-code-or1k/except-mc.ld (working copy)
@@ -60,11 +60,24 @@
_dst_end = .;
} > ram
- .bss :
+
+ .bss :
{
*(.bss)
+
+ /* WARNING about section size alignment:
+ The start-up assembly code can only clear BSS section sizes which
are aligned to 4 bytes.
+ However, the size of the BSS section may not be aligned, therefore
up to 3 bytes more
+ could be zeroed on start-up. This is normally not an issue, as the
start of the next section
+ is usually aligned too, so those extra bytes should be just
padding. I did try the following
+ trick to align the BSS section size, to no avail:
+ . = ALIGN(., 4); */
} > ram
+ _bstart = ADDR(.bss);
+ _bend = _bstart + SIZEOF(.bss);
+
+
.stack ALIGN(0x10) (NOLOAD):
{
*(.stack)
Index: testsuite/test-code-or1k/except-test/except-test-s.S
===================================================================
--- testsuite/test-code-or1k/except-test/except-test-s.S (revision 787)
+++ testsuite/test-code-or1k/except-test/except-test-s.S (working copy)
@@ -26,6 +26,7 @@
--------------------------------------------------------------------------*/
#include "spr-defs.h"
+#include "support.inc"
#include "board.h"
#define reset main
@@ -380,19 +381,8 @@
l.ori r1,r1,lo(stack)
l.ori r2,r1,0
-bss_clear:
- /* Clear BSS */
- l.movhi r3, hi(_bstart)
- l.ori r3, r3, lo(_bstart)
- l.movhi r4, hi(_bend)
- l.ori r4, r4, lo(_bend)
-bss_clear_loop:
- l.sw 0(r3), r0
- l.sfgtu r3, r4
- l.bnf bss_clear_loop
- l.addi r3, r3, 4
+ CLEAR_BSS
-
l.movhi r3,hi(reset)
l.ori r3,r3,lo(reset)
l.jr r3
Index: testsuite/test-code-or1k/except/except.S
===================================================================
--- testsuite/test-code-or1k/except/except.S (revision 787)
+++ testsuite/test-code-or1k/except/except.S (working copy)
@@ -27,6 +27,7 @@
/* Support file for c based tests */
#include "spr-defs.h"
+#include "support.inc"
#define reset reset
@@ -284,6 +285,8 @@
l.ori r1,r1,lo(stack)
l.ori r2,r1, 0
+ CLEAR_BSS
+
/* Call reset() function, in support library, which calls main() */
l.movhi r4,hi(reset)
l.ori r4,r4,lo(reset)
Index: testsuite/test-code-or1k/fp/fp.S
===================================================================
--- testsuite/test-code-or1k/fp/fp.S (revision 787)
+++ testsuite/test-code-or1k/fp/fp.S (working copy)
@@ -41,6 +41,7 @@
#include "spr-defs.h"
+#include "support.inc"
#include "board.h"
/* ----------------------------------------------------------------------------
@@ -359,6 +360,8 @@
l.movhi r1,hi(_stack) /* Set up the stack */
l.ori r1,r1,lo(_stack)
+
+ CLEAR_BSS
l.movhi r3,hi(start) /* Jump to test start */
l.ori r3,r3,lo(start)
Index: testsuite/test-code-or1k/inst-set-test/inst-set-test.S
===================================================================
--- testsuite/test-code-or1k/inst-set-test/inst-set-test.S (revision 787)
+++ testsuite/test-code-or1k/inst-set-test/inst-set-test.S (working copy)
@@ -79,6 +79,8 @@
l.movhi r1,hi(_stack) /* Set up the stack */
l.ori r1,r1,lo(_stack)
+ CLEAR_BSS
+
l.j _start /* Jump to the start of code */
l.nop
Index: testsuite/test-code-or1k/inst-set-test/inst-set-test.h
===================================================================
--- testsuite/test-code-or1k/inst-set-test/inst-set-test.h (revision 787)
+++ testsuite/test-code-or1k/inst-set-test/inst-set-test.h (working copy)
@@ -23,6 +23,7 @@
#include "spr-defs.h"
+#include "support.inc"
#include "board.h"
/* ----------------------------------------------------------------------------
Index: testsuite/test-code-or1k/inst-set-test/inst-set-test.ld
===================================================================
--- testsuite/test-code-or1k/inst-set-test/inst-set-test.ld (revision 787)
+++ testsuite/test-code-or1k/inst-set-test/inst-set-test.ld (working copy)
@@ -54,11 +54,24 @@
*(.data)
} > ram
- .bss :
- {
- *(.bss)
- } > ram
+ .bss :
+ {
+ *(.bss)
+
+ /* WARNING about section size alignment:
+ The start-up assembly code can only clear BSS section sizes which are
aligned to 4 bytes.
+ However, the size of the BSS section may not be aligned, therefore up
to 3 bytes more
+ could be zeroed on start-up. This is normally not an issue, as the
start of the next section
+ is usually aligned too, so those extra bytes should be just padding. I
did try the following
+ trick to align the BSS section size, to no avail:
+ . = ALIGN(., 4); */
+ } > ram
+
+ _bstart = ADDR(.bss);
+ _bend = _bstart + SIZEOF(.bss);
+
+
.stack ALIGN (0x10) (NOLOAD) :
{
*(.stack)
Index: testsuite/test-code-or1k/mc-common/except-mc.S
===================================================================
--- testsuite/test-code-or1k/mc-common/except-mc.S (revision 787)
+++ testsuite/test-code-or1k/mc-common/except-mc.S (working copy)
@@ -27,6 +27,7 @@
/* Support file for c based tests */
#include "spr-defs.h"
+#include "support.inc"
#define reset reset
@@ -92,39 +93,6 @@
l.j init_mc
l.nop
-start: l.movhi r1,hi(stack)
- l.ori r1,r1,lo(stack)
-
- /* Check if this is RTL version */
- l.lbz r3,0(r0)
- l.sfeqi r3,0xff
- l.bf 2f
- l.nop
- l.movhi r3,hi(_src_beg)
- l.ori r3,r3,lo(_src_beg)
- l.movhi r4,hi(_dst_beg)
- l.ori r4,r4,lo(_dst_beg)
- l.movhi r5,hi(_dst_end)
- l.ori r5,r5,lo(_dst_end)
- l.sub r5,r5,r4
- l.sfeqi r5,0
- l.bf 2f
- l.nop
-1: l.lwz r6,0(r3)
- l.sw 0(r4),r6
- l.addi r3,r3,4
- l.addi r4,r4,4
- l.addi r5,r5,-4
- l.sfgtsi r5,0
- l.bf 1b
- l.nop
-
-2:
- l.movhi r2,hi(reset)
- l.ori r2,r2,lo(reset)
- l.jr r2
- l.nop
-
.org 0x200
buserr_vector:
l.addi r1,r1,-116
@@ -424,5 +392,38 @@
l.xor r2,r2,r2
l.xor r3,r3,r3
- l.j start
+
+start: l.movhi r1,hi(stack)
+ l.ori r1,r1,lo(stack)
+
+ CLEAR_BSS
+
+ /* Check if this is RTL version */
+ l.lbz r3,0(r0)
+ l.sfeqi r3,0xff
+ l.bf 2f
l.nop
+ l.movhi r3,hi(_src_beg)
+ l.ori r3,r3,lo(_src_beg)
+ l.movhi r4,hi(_dst_beg)
+ l.ori r4,r4,lo(_dst_beg)
+ l.movhi r5,hi(_dst_end)
+ l.ori r5,r5,lo(_dst_end)
+ l.sub r5,r5,r4
+ l.sfeqi r5,0
+ l.bf 2f
+ l.nop
+1: l.lwz r6,0(r3)
+ l.sw 0(r4),r6
+ l.addi r3,r3,4
+ l.addi r4,r4,4
+ l.addi r5,r5,-4
+ l.sfgtsi r5,0
+ l.bf 1b
+ l.nop
+
+2:
+ l.movhi r2,hi(reset)
+ l.ori r2,r2,lo(reset)
+ l.jr r2
+ l.nop
Index: testsuite/test-code-or1k/support/support.inc
===================================================================
--- testsuite/test-code-or1k/support/support.inc (revision 0)
+++ testsuite/test-code-or1k/support/support.inc (revision 0)
@@ -0,0 +1,45 @@
+/* support.inc -- Assembler include file for the Or1ksim test suite.
+
+ Copyright (C) 2012 R. Diez
+
+ This file is part of OpenRISC 1000 Architectural Simulator.
+
+ This program is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the Free
+ Software Foundation; either version 3 of the License, or (at your option)
+ any later version.
+
+ This program is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+// Clear the BSS section on start-up.
+// Overwrites registers R3 and R4.
+
+.macro CLEAR_BSS
+
+ l.movhi r3, hi(_bstart)
+ l.ori r3, r3, lo(_bstart)
+ l.movhi r4, hi(_bend)
+ l.ori r4, r4, lo(_bend)
+
+ l.sfgeu r3, r4
+ l.bf bss_is_empty
+ l.nop 0
+
+bss_clear_loop:
+ // Possible optimisation to investigate: move "l.sw 0(r3), r0" to the
jump delay slot as "l.sw -4(r3), r0" or similar.
+ l.sw 0(r3), r0
+ l.addi r3, r3, 4
+ l.sfgtu r4, r3
+ l.bf bss_clear_loop
+ l.nop 0
+
+bss_is_empty:
+
+.endm
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