Hi John, Step 1: Locate the most up-to-date versions of the or1200, its documents > and the wishbone spec and copy them into a new repository. Freeze the > originals so that nothing we do will impact the users. The only changes > that we will make to the "official" release are critical bugs that are also > made to the release candidate as well. > > The SVN versions on OpenCores are the most up-to-date, so those are the ones we will use. (the orpsoc copy of the RTL is kept in sync with the upstream). One of the points I had about making a release with what we got is that we should release basically what we have now. That will decrease the impact on the users, and after the release, whoever wants a stable copy can use the tagged one, perhaps with critical bug fixes, while we keep developing the next version in trunk.
> Step 2: Create a tool flow for simulation and linting and copy over as > many or1200 sims as we can find. We need to create a robust suite capable > of verifying the entire design. > > Proper testing would be highly appreciated, but for this release, I think we could do with the tests we have now, as long as we don't change things too much. The current code has had a lot of usage, and that could spare us from some of the testing. I'm well aware that this is not how we should do it in the future, but I think it's more important to have a good enough release now, then a perfect release later on. Basically, we need to get better at release management, and this could be a start. The version after that could be perfect :) > Step 3: Let developers try it and discuss what works and what doesn't. > Anyone can modify a cloned database to show their proposals in action. The > stuff that works gets pulled back into the golden copy. > > After we do an RTL freeze, we should definitely put it under some heavy testing with all the test cases we can come up with. Any critical problems that comes up during testing should be discussed and solved -- Olof Kindgren ______________________________________________ ORSoC Website: www.orsoc.se Email: [email protected] ______________________________________________ FPGA, ASIC, DSP - embedded SoC design
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